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| author | gatecat <gatecat@ds0.me> | 2021-03-29 18:23:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-29 18:23:16 +0100 |
| commit | 692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 (patch) | |
| tree | ebe474f5cacc1206b083c7a09e77d431b4a61e61 /fpga_interchange/examples/tests/ram/run.tcl | |
| parent | 4419c36db5556d2a7f600517d6a4b5673067579d (diff) | |
| parent | f33d02dca9f6080c2497a4e058554c9908677888 (diff) | |
| download | nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.tar.gz nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.tar.bz2 nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.zip | |
Merge pull request #645 from litghost/add_counter_and_ram
FPGA interchange: Add counter and ram tests
Diffstat (limited to 'fpga_interchange/examples/tests/ram/run.tcl')
| -rw-r--r-- | fpga_interchange/examples/tests/ram/run.tcl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/ram/run.tcl b/fpga_interchange/examples/tests/ram/run.tcl new file mode 100644 index 00000000..79321139 --- /dev/null +++ b/fpga_interchange/examples/tests/ram/run.tcl @@ -0,0 +1,17 @@ +yosys -import + +foreach src $::env(SOURCES) { + read_verilog $src +} + +synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp +techmap -map $::env(TECHMAP) + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) |