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authorgatecat <gatecat@ds0.me>2021-06-01 11:45:34 +0100
committerGitHub <noreply@github.com>2021-06-01 11:45:34 +0100
commit665ab09d209d9aa9be4e67ef9401b8c7768e8f3c (patch)
treedd0776a3d57a596b15a3c6c52f7d203cb1094cc1 /fpga_interchange/examples/tests/wire/lifcl40evn.xdc
parent24ae205f20f0e1a0326e48002ab14d5bacfca1ef (diff)
parent0426ba4e877c0ec1130d8ab7bc74e70cc4e406bf (diff)
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Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40
interchange: Add LIFCL-40 EVN tests
Diffstat (limited to 'fpga_interchange/examples/tests/wire/lifcl40evn.xdc')
-rw-r--r--fpga_interchange/examples/tests/wire/lifcl40evn.xdc5
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/wire/lifcl40evn.xdc b/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
new file mode 100644
index 00000000..c1a87488
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN G19 [get_ports i]
+set_property PACKAGE_PIN E17 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]