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authorAlessandro Comodi <acomodi@antmicro.com>2021-03-12 13:53:09 +0100
committerAlessandro Comodi <acomodi@antmicro.com>2021-03-16 15:39:01 +0100
commit77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f (patch)
tree143ce61b476d33d2b0ddd63d5beb872f5d077949 /fpga_interchange/examples/tests/wire
parent6a08b0d733e928e5e7c180dee21829f7db2d9ccf (diff)
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fpga_interchange: tests: add cmake functions
Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/examples/tests/wire')
-rw-r--r--fpga_interchange/examples/tests/wire/CMakeLists.txt17
-rw-r--r--fpga_interchange/examples/tests/wire/run.tcl14
-rw-r--r--fpga_interchange/examples/tests/wire/wire.v5
-rw-r--r--fpga_interchange/examples/tests/wire/wire.xdc5
4 files changed, 41 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt
new file mode 100644
index 00000000..7736877f
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt
@@ -0,0 +1,17 @@
+add_interchange_test(
+ name wire_basys3
+ part xc7a35tcpg236-1
+ package cpg236
+ tcl run.tcl
+ xdc wire.xdc
+ sources wire.v
+)
+
+add_interchange_test(
+ name wire_arty
+ part xc7a35tcsg324-1
+ package csg324
+ tcl run.tcl
+ xdc wire.xdc
+ sources wire.v
+)
diff --git a/fpga_interchange/examples/tests/wire/run.tcl b/fpga_interchange/examples/tests/wire/run.tcl
new file mode 100644
index 00000000..b8d0df72
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/wire/wire.v b/fpga_interchange/examples/tests/wire/wire.v
new file mode 100644
index 00000000..429d05ff
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/wire.v
@@ -0,0 +1,5 @@
+module top(input i, output o);
+
+assign o = i;
+
+endmodule
diff --git a/fpga_interchange/examples/tests/wire/wire.xdc b/fpga_interchange/examples/tests/wire/wire.xdc
new file mode 100644
index 00000000..c923f0fc
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/wire.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN N16 [get_ports i]
+set_property PACKAGE_PIN N15 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]