Merge pull request #576 from litghost/add_cell_bel_pin_mapping

Complete FPGA interchange Arch to the point where it can route a wire

14 files changed, 289 insertions, 0 deletions

diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile
new file mode 100644
index 00000000..cf82013b
--- /dev/null
+++ b/fpga_interchange/examples/archcheck/Makefile
@@ -0,0 +1,16 @@
+include ../common.mk
+
+PACKAGE := csg324
+
+.PHONY: check check_test_data
+
+check: check_test_data
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--package $(PACKAGE) \
+		--test
+
+check_test_data:
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--run $(NEXTPNR_PATH)/python/check_arch_api.py
diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml
new file mode 100644
index 00000000..b41112cf
--- /dev/null
+++ b/fpga_interchange/examples/archcheck/test_data.yaml
@@ -0,0 +1,7 @@
+pip_test:
+    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+      dst_wire: SLICE_X15Y93.SLICEL/D3
+bel_pin_test:
+    - bel: SLICE_X15Y93.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X15Y93.SLICEL/D3
diff --git a/fpga_interchange/examples/common.mk b/fpga_interchange/examples/common.mk
new file mode 100644
index 00000000..ce558472
--- /dev/null
+++ b/fpga_interchange/examples/common.mk
@@ -0,0 +1,8 @@
+NEXTPNR_PATH := $(realpath ../../..)
+NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
+BBA_PATH := $(realpath ..)/create_bba/build/xc7a35.bin
+
+RAPIDWRIGHT_PATH := $(realpath ..)/create_bba/build/RapidWright
+INTERCHANGE_PATH := $(realpath ..)/create_bba/build/fpga-interchange-schema/interchange
+
+DEVICE := $(realpath ..)/create_bba/build/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device
diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile
new file mode 100644
index 00000000..3033daca
--- /dev/null
+++ b/fpga_interchange/examples/create_bba/Makefile
@@ -0,0 +1,91 @@
+#
+#  nextpnr -- Next Generation Place and Route
+#
+#  Copyright (C) 2021  Symbiflow Authors
+#
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+# This Makefile provides a streamlined way to create an example
+# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts.
+#
+# FPGA interchange device database is generated via RapidWright.
+#
+# Currently FPGA interchange physical netlist (e.g. place and route route) to
+# FASM support is not done, so bitstream generation relies on RapidWright to
+# convert FPGA interchange logical and physical netlist into a Vivado DCP.
+
+include ../common.mk
+
+.DELETE_ON_ERROR:
+
+.PHONY: all chipdb
+
+all: chipdb
+
+build:
+	mkdir build
+
+build/RapidWright: | build
+	# FIXME: Update URL / branch as fixes are merged upstream and / or
+	# interchange branch on Xilinx/RapidWright is merged to master branch.
+	#
+	#cd build && git clone -b interchange https://github.com/Xilinx/RapidWright.git
+	cd build && git clone -b move_strlist https://github.com/litghost/RapidWright.git
+
+build/env: | build
+	python3 -mvenv build/env
+
+build/python-fpga-interchange: | build
+	cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git
+
+build/fpga-interchange-schema: | build
+	cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git
+
+build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright
+	source build/env/bin/activate && \
+		cd build/python-fpga-interchange/ && \
+		pip install -r requirements.txt
+	touch build/.setup
+
+$(NEXTPNR_PATH)/build:
+	mkdir $(NEXTPNR_PATH)/build
+
+$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
+	cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
+	make -j -C $(NEXTPNR_PATH)/build
+
+$(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
+	mkdir -p build/nextpnr/fpga_interchange
+	source build/env/bin/activate && \
+		cd build/python-fpga-interchange/ && \
+		make \
+		-f Makefile.rapidwright \
+		NEXTPNR_PATH=$(realpath .)/build/nextpnr \
+		RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
+		INTERCHANGE_PATH=$(INTERCHANGE_PATH)
+
+$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba
+	$(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
+
+chipdb: $(BBA_PATH)
+
+test: chipdb
+	$(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
+		--chipdb $(BBA_PATH) \
+		--package csg324 \
+		--test
+
+clean:
+	rm -rf build
diff --git a/fpga_interchange/examples/create_bba/README.md b/fpga_interchange/examples/create_bba/README.md
new file mode 100644
index 00000000..d2ca5188
--- /dev/null
+++ b/fpga_interchange/examples/create_bba/README.md
@@ -0,0 +1,40 @@
+## Makefile-driven BBA creation
+
+This Makefile will generate a Xilinx A35 chipdb if java, capnproto and
+capnproto-java are installed.
+
+### Installing dependencies
+
+Install java and javac if not already installed:
+```
+# Or equivalent for your local system.
+sudo apt-get install openjdk-10-jdk
+```
+
+Install capnproto if not already installed:
+```
+# Or equivalent for your local system.
+sudo apt-get install capnproto libcapnp-dev
+```
+
+Install capnproto-java if not already installed:
+```
+git clone https://github.com/capnproto/capnproto-java.git
+cd capnproto-java
+make
+sudo make install
+```
+
+### Instructions
+
+Once dependencies are installed, just run "make".  This should download
+remaining dependencies and build the chipdb and build nextpnr if not built.
+
+#### Re-building the chipdb
+
+```
+# Remove the text BBA
+rm build/nextpnr/fpga_interchange/chipdb.bba
+# Build the BBA
+make
+```
diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile
new file mode 100644
index 00000000..54fc8994
--- /dev/null
+++ b/fpga_interchange/examples/lut/Makefile
@@ -0,0 +1,8 @@
+DESIGN := lut
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/lut.json: lut.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v
new file mode 100644
index 00000000..ca18e665
--- /dev/null
+++ b/fpga_interchange/examples/lut/lut.v
@@ -0,0 +1,5 @@
+module top(input i0, input i1, output o);
+
+assign o = i0 | i1;
+
+endmodule
diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc
new file mode 100644
index 00000000..4f390f25
--- /dev/null
+++ b/fpga_interchange/examples/lut/lut.xdc
@@ -0,0 +1,7 @@
+set_property PACKAGE_PIN N16 [get_ports i0]
+set_property PACKAGE_PIN N15 [get_ports i1]
+set_property PACKAGE_PIN M17 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i0]
+set_property IOSTANDARD LVCMOS33 [get_ports i1]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl
new file mode 100644
index 00000000..1edd8bb7
--- /dev/null
+++ b/fpga_interchange/examples/lut/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog lut.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/lut.json
diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk
new file mode 100644
index 00000000..819cdb1f
--- /dev/null
+++ b/fpga_interchange/examples/template.mk
@@ -0,0 +1,64 @@
+include ../common.mk
+
+.DELETE_ON_ERROR:
+.PHONY: all debug clean netlist_yaml phys_yaml
+
+all: build/$(DESIGN).dcp
+
+build:
+	mkdir build
+
+build/$(DESIGN).netlist: build/$(DESIGN).json
+	/usr/bin/time -v python3 -mfpga_interchange.yosys_json \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--device $(DEVICE) \
+		--top $(DESIGN_TOP) \
+		build/$(DESIGN).json \
+		build/$(DESIGN).netlist
+
+build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist
+	/usr/bin/time -v python3 -mfpga_interchange.convert \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--schema logical \
+		--input_format capnp \
+		--output_format yaml \
+		build/$(DESIGN).netlist \
+		build/$(DESIGN)_netlist.yaml
+
+netlist_yaml: build/$(DESIGN)_netlist.yaml
+
+build/$(DESIGN).phys: build/$(DESIGN).netlist
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE) \
+
+build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
+	/usr/bin/time -v python3 -mfpga_interchange.convert \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--schema physical \
+		--input_format capnp \
+		--output_format yaml \
+		build/$(DESIGN).phys \
+		build/$(DESIGN)_phys.yaml
+
+phys_yaml: build/$(DESIGN)_phys.yaml
+
+debug: build/$(DESIGN).netlist
+	gdb --args $(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE)
+
+build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
+	RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
+		$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
+		com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
+		build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp
+
+clean:
+	rm -rf build
diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile
new file mode 100644
index 00000000..49194f53
--- /dev/null
+++ b/fpga_interchange/examples/wire/Makefile
@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/wire/run.tcl b/fpga_interchange/examples/wire/run.tcl
new file mode 100644
index 00000000..9127be20
--- /dev/null
+++ b/fpga_interchange/examples/wire/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog wire.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/wire.json
diff --git a/fpga_interchange/examples/wire/wire.v b/fpga_interchange/examples/wire/wire.v
new file mode 100644
index 00000000..429d05ff
--- /dev/null
+++ b/fpga_interchange/examples/wire/wire.v
@@ -0,0 +1,5 @@
+module top(input i, output o);
+
+assign o = i;
+
+endmodule
diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc
new file mode 100644
index 00000000..e1fce5f0
--- /dev/null
+++ b/fpga_interchange/examples/wire/wire.xdc
@@ -0,0 +1,2 @@
+set_property PACKAGE_PIN N16 [get_ports i]
+set_property PACKAGE_PIN N15 [get_ports o]