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| author | gatecat <gatecat@ds0.me> | 2021-04-09 10:23:56 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-04-09 10:26:32 +0100 |
| commit | 93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0 (patch) | |
| tree | e6dde27f493acf1f76b8be8c438ba6aa09147318 /fpga_interchange/lookahead.cc | |
| parent | 581682a08e6113eb8abfaf9e690e399e350e982c (diff) | |
| download | nextpnr-93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0.tar.gz nextpnr-93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0.tar.bz2 nextpnr-93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0.zip | |
interchange: Disambiguate cell and bel pins when creating Vcc ties
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/lookahead.cc')
0 files changed, 0 insertions, 0 deletions