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| author | Maciej Kurc <mkurc@antmicro.com> | 2021-07-09 15:40:06 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2021-07-16 12:51:28 +0200 |
| commit | d52516756cf32ecb53b75e8a6f032ebeeb427a71 (patch) | |
| tree | 177e69eab87605db020a66ae1cf5a0494e6c9151 /fpga_interchange/luts.h | |
| parent | c696e885736ed052bd1d5e8fd91b42ee3bc6af9f (diff) | |
| download | nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.tar.gz nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.tar.bz2 nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.zip | |
Working site LUT mapping cache
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'fpga_interchange/luts.h')
| -rw-r--r-- | fpga_interchange/luts.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h index cbb817c9..7b6ce758 100644 --- a/fpga_interchange/luts.h +++ b/fpga_interchange/luts.h @@ -31,6 +31,8 @@ NEXTPNR_NAMESPACE_BEGIN struct CellInfo; struct Context; +struct SiteLutMappingResult; + enum LogicLevel { LL_Zero, @@ -66,6 +68,14 @@ struct LutBel int32_t max_pin; }; +struct SiteLutMapping +{ + struct LutCellMapping { + LutCell lut_cell; + }; +}; + + // Work forward from cell definition and cell -> bel pin map and check that // equation is valid. void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cell_to_bel_map, const LutBel &lut_bel, @@ -89,7 +99,7 @@ struct LutMapper std::vector<CellInfo *> cells; - bool remap_luts(const Context *ctx, pool<const LutBel *, hash_ptr_ops> *blocked_luts); + bool remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping, pool<const LutBel *, hash_ptr_ops> *blocked_luts); // Determine which wires given the current mapping must be tied to the // default constant. |