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author | David Shah <dave@ds0.me> | 2021-02-05 19:15:29 +0000 |
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committer | GitHub <noreply@github.com> | 2021-02-05 19:15:29 +0000 |
commit | 8b4163b77c667c4f2a29e48adab96abc2a83b03d (patch) | |
tree | f0ebf104fd3b9a5f1752698b3df4e5c2f2af3304 /fpga_interchange/main.cc | |
parent | b0f9b7834e4cb035d1fd60f0fa1948c0fdfa233c (diff) | |
parent | a0ee42833b774483f9b2fc35109f7ec948dbdc9b (diff) | |
download | nextpnr-8b4163b77c667c4f2a29e48adab96abc2a83b03d.tar.gz nextpnr-8b4163b77c667c4f2a29e48adab96abc2a83b03d.tar.bz2 nextpnr-8b4163b77c667c4f2a29e48adab96abc2a83b03d.zip |
Merge pull request #567 from litghost/initial_fpga_interchange
Initial FPGA interchange arch
Diffstat (limited to 'fpga_interchange/main.cc')
-rw-r--r-- | fpga_interchange/main.cc | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/fpga_interchange/main.cc b/fpga_interchange/main.cc new file mode 100644 index 00000000..1f98b186 --- /dev/null +++ b/fpga_interchange/main.cc @@ -0,0 +1,84 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 Claire Wolf <claire@symbioticeda.com> + * Copyright (C) 2021 Symbiflow Authors + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifdef MAIN_EXECUTABLE + +#include <fstream> +#include "command.h" +#include "design_utils.h" +#include "jsonwrite.h" +#include "log.h" +#include "timing.h" + +USING_NEXTPNR_NAMESPACE + +class FpgaInterchangeCommandHandler : public CommandHandler +{ + public: + FpgaInterchangeCommandHandler(int argc, char **argv); + virtual ~FpgaInterchangeCommandHandler(){}; + std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override; + void setupArchContext(Context *ctx) override{}; + void customBitstream(Context *ctx) override; + void customAfterLoad(Context *ctx) override; + + protected: + po::options_description getArchOptions() override; +}; + +FpgaInterchangeCommandHandler::FpgaInterchangeCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {} + +po::options_description FpgaInterchangeCommandHandler::getArchOptions() +{ + po::options_description specific("Architecture specific options"); + specific.add_options()("chipdb", po::value<std::string>(), "name of chip database binary"); + specific.add_options()("xdc", po::value<std::vector<std::string>>(), "XDC-style constraints file"); + specific.add_options()("phys", po::value<std::string>(), "FPGA interchange Physical netlist to write"); + + return specific; +} + +void FpgaInterchangeCommandHandler::customBitstream(Context *ctx) +{ + if (vm.count("phys")) { + std::string filename = vm["phys"].as<std::string>(); + ctx->write_physical_netlist(filename); + } +} + +std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(std::unordered_map<std::string, Property> &values) +{ + ArchArgs chipArgs; + if (!vm.count("chipdb")) { + log_error("chip database binary must be provided\n"); + } + chipArgs.chipdb = vm["chipdb"].as<std::string>(); + return std::unique_ptr<Context>(new Context(chipArgs)); +} + +void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx) {} + +int main(int argc, char *argv[]) +{ + FpgaInterchangeCommandHandler handler(argc, argv); + return handler.exec(); +} + +#endif |