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authorgatecat <gatecat@ds0.me>2021-03-29 18:23:16 +0100
committerGitHub <noreply@github.com>2021-03-29 18:23:16 +0100
commit692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 (patch)
treeebe474f5cacc1206b083c7a09e77d431b4a61e61 /fpga_interchange/site_arch.impl.h
parent4419c36db5556d2a7f600517d6a4b5673067579d (diff)
parentf33d02dca9f6080c2497a4e058554c9908677888 (diff)
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Merge pull request #645 from litghost/add_counter_and_ram
FPGA interchange: Add counter and ram tests
Diffstat (limited to 'fpga_interchange/site_arch.impl.h')
-rw-r--r--fpga_interchange/site_arch.impl.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/fpga_interchange/site_arch.impl.h b/fpga_interchange/site_arch.impl.h
index 0be298c9..a471b690 100644
--- a/fpga_interchange/site_arch.impl.h
+++ b/fpga_interchange/site_arch.impl.h
@@ -295,6 +295,25 @@ inline bool SiteArch::canInvert(const SitePip &site_pip) const
return bel_data.non_inverting_pin == pip_data.extra_data && bel_data.inverting_pin == pip_data.extra_data;
}
+inline PhysicalNetlist::PhysNetlist::NetType SiteArch::prefered_constant_net_type(const SitePip &site_pip) const
+{
+ // FIXME: Implement site port overrides from chipdb once available.
+ IdString prefered_constant_net(ctx->chip_info->constants->best_constant_net);
+ IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
+ IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
+
+ if (prefered_constant_net == IdString()) {
+ return PhysicalNetlist::PhysNetlist::NetType::SIGNAL;
+ } else if (prefered_constant_net == gnd_net_name) {
+ return PhysicalNetlist::PhysNetlist::NetType::GND;
+ } else if (prefered_constant_net == vcc_net_name) {
+ return PhysicalNetlist::PhysNetlist::NetType::VCC;
+ } else {
+ log_error("prefered_constant_net %s is not the GND (%s) or VCC(%s) net?\n", prefered_constant_net.c_str(ctx),
+ gnd_net_name.c_str(ctx), vcc_net_name.c_str(ctx));
+ }
+}
+
NEXTPNR_NAMESPACE_END
#endif /* SITE_ARCH_H */