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authorAlessandro Comodi <acomodi@antmicro.com>2021-05-12 18:25:47 +0200
committerAlessandro Comodi <acomodi@antmicro.com>2021-05-13 11:00:42 +0200
commit8c468acff8900f40e909882cfbf9381a59199b79 (patch)
treebd1b8dba70b86034fae4adb61f1cb2d10140fb49 /fpga_interchange/site_router.h
parentfd93697a2d4eca02fc5091a15a497f7a761f251a (diff)
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interchange: site router: add valid pips list to check during routing
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/site_router.h')
-rw-r--r--fpga_interchange/site_router.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga_interchange/site_router.h b/fpga_interchange/site_router.h
index cf17026d..3222669a 100644
--- a/fpga_interchange/site_router.h
+++ b/fpga_interchange/site_router.h
@@ -38,6 +38,7 @@ struct SiteRouter
SiteRouter(int16_t site) : site(site), dirty(false), site_ok(true) {}
std::unordered_set<CellInfo *> cells_in_site;
+ std::vector<PipId> valid_pips;
const int16_t site;
mutable bool dirty;