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| author | gatecat <gatecat@ds0.me> | 2021-02-15 09:38:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-15 09:38:22 +0000 |
| commit | 1b6cdce9251d42236a3db0314e84d6a3e3f06408 (patch) | |
| tree | be3b382420edd6cb1f1b6203f7ac518c7aeb4a4f /fpga_interchange | |
| parent | f1ccc0e20531f63355e3da7c6c5f4f39a684fa3f (diff) | |
| parent | 7c7d69e1d2030dc983d0ddbc0e04f6765d51bbbc (diff) | |
| download | nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.tar.gz nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.tar.bz2 nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.zip | |
Merge pull request #575 from YosysHQ/gatecat/belpin-2
Support for cell pin to bel pin mappings
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 435bb93d..886978f1 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -661,6 +661,7 @@ struct ArchRanges using TileBelsRangeT = BelRange; using BelAttrsRangeT = std::vector<std::pair<IdString, std::string>>; using BelPinsRangeT = IdStringRange; + using CellBelPinRangeT = std::array<IdString, 1>; // Wires using AllWiresRangeT = WireRange; using DownhillPipRangeT = DownhillPipRange; @@ -866,6 +867,8 @@ struct Arch : ArchAPI<ArchRanges> return str_range; } + std::array<IdString, 1> getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override { return {pin}; } + // ------------------------------------------------- WireId getWireByName(IdStringList name) const override; |