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| author | gatecat <gatecat@ds0.me> | 2021-05-16 16:25:05 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-16 16:25:05 +0100 |
| commit | 5a41d2070c8a7c065d4e3fbfb70b3a3fbd19b319 (patch) | |
| tree | 62ee961ac0c4b8da9a3515b4236b39a6c5f7ebc7 /fpga_interchange | |
| parent | 179ae683cccede93dae9ef76ab82bd2617b224c7 (diff) | |
| download | nextpnr-5a41d2070c8a7c065d4e3fbfb70b3a3fbd19b319.tar.gz nextpnr-5a41d2070c8a7c065d4e3fbfb70b3a3fbd19b319.tar.bz2 nextpnr-5a41d2070c8a7c065d4e3fbfb70b3a3fbd19b319.zip | |
Run clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.cc | 3 | ||||
| -rw-r--r-- | fpga_interchange/site_router.cc | 9 |
2 files changed, 7 insertions, 5 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index a05878f6..e94dab10 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -733,7 +733,6 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile; int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile; - int src_x, src_y; get_tile_x_y(src_tile, &src_x, &src_y); @@ -1804,7 +1803,7 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const const BelInfoPOD &bel_data = tile_type.bel_data[net->driver.cell->bel.index]; const SiteRouter &site_router = get_site_status(tile_status_iter->second, bel_data); - const auto& pips = site_router.valid_pips; + const auto &pips = site_router.valid_pips; auto result = std::find(pips.begin(), pips.end(), pip); if (result != pips.end()) { valid_pip = true; diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 9081a57e..f4d65958 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -964,7 +964,8 @@ static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetI } } -static void apply_routing(Context *ctx, const SiteArch &site_arch, HashTables::HashSet<std::pair<IdString, int32_t>, PairHash> &lut_thrus) +static void apply_routing(Context *ctx, const SiteArch &site_arch, + HashTables::HashSet<std::pair<IdString, int32_t>, PairHash> &lut_thrus) { IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name); NetInfo *gnd_net = ctx->nets.at(gnd_net_name).get(); @@ -1092,7 +1093,8 @@ static void block_lut_outputs(SiteArch *site_arch, // Recursively visit downhill PIPs until a SITE_PORT_SINK is reached. // Marks all PIPs for all valid paths. -static bool visit_downhill_pips(const SiteArch *site_arch, const SiteWire &site_wire, std::vector<PipId> &valid_pips) { +static bool visit_downhill_pips(const SiteArch *site_arch, const SiteWire &site_wire, std::vector<PipId> &valid_pips) +{ bool valid_path_exists = false; for (SitePip site_pip : site_arch->getPipsDownhill(site_wire)) { const SiteWire &dst_wire = site_arch->getPipDstWire(site_pip); @@ -1114,7 +1116,8 @@ static bool visit_downhill_pips(const SiteArch *site_arch, const SiteWire &site_ // Checks all downhill PIPs starting from driver wires. // All valid PIPs are stored and returned in a vector. -static void check_downhill_pips(Context *ctx, const SiteArch *site_arch, std::vector<PipId> &valid_pips) { +static void check_downhill_pips(Context *ctx, const SiteArch *site_arch, std::vector<PipId> &valid_pips) +{ auto &cells_in_site = site_arch->site_info->cells_in_site; for (auto &net_pair : site_arch->nets) { |