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| author | gatecat <gatecat@ds0.me> | 2021-06-28 16:27:04 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-28 16:27:04 +0100 |
| commit | 78c965141f25892986589976476c237372d9406d (patch) | |
| tree | 23cecdebebc4501b0330a9346ae8ae5481a937d4 /fpga_interchange | |
| parent | 7115dd3393a5d2de986521eb8776b072fd562aff (diff) | |
| parent | 65a4bce9adae909c9efec6cea12e53983b5c5779 (diff) | |
| download | nextpnr-78c965141f25892986589976476c237372d9406d.tar.gz nextpnr-78c965141f25892986589976476c237372d9406d.tar.bz2 nextpnr-78c965141f25892986589976476c237372d9406d.zip | |
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output
interchange: Allow site wires driven by more than one bel
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/pseudo_pip_model.cc | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc index 2441c8a9..39718c65 100644 --- a/fpga_interchange/pseudo_pip_model.cc +++ b/fpga_interchange/pseudo_pip_model.cc @@ -63,8 +63,6 @@ void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type) sites.emplace(wire_data.site); - int32_t driver_bel = -1; - int32_t output_pin = -1; for (const BelPortPOD &bel_pin : wire_data.bel_pins) { const BelInfoPOD &bel_data = type_data.bel_data[bel_pin.bel_index]; if (bel_data.synthetic != NOT_SYNTH) { @@ -92,18 +90,9 @@ void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type) continue; } - // Each site wire should have 1 driver! - NPNR_ASSERT(driver_bel == -1); - driver_bel = bel_pin.bel_index; - output_pin = bel_pin_idx; - } - - if (driver_bel != -1) { - NPNR_ASSERT(output_pin != -1); PseudoPipBel bel; - bel.bel_index = driver_bel; - bel.output_bel_pin = output_pin; - + bel.bel_index = bel_pin.bel_index; + bel.output_bel_pin = bel_pin_idx; pseudo_pip_bels.push_back(bel); } } |