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| author | Maciej Kurc <mkurc@antmicro.com> | 2021-07-16 15:16:31 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2021-07-16 15:16:31 +0200 |
| commit | c95aa86a8e4fe290bdb030977b7ca40e619a0c30 (patch) | |
| tree | c297db2571d5587b763dbda60ac9048b7260041f /fpga_interchange | |
| parent | 857961a6bb9302847ecf605971015f1610dae476 (diff) | |
| download | nextpnr-c95aa86a8e4fe290bdb030977b7ca40e619a0c30.tar.gz nextpnr-c95aa86a8e4fe290bdb030977b7ca40e619a0c30.tar.bz2 nextpnr-c95aa86a8e4fe290bdb030977b7ca40e619a0c30.zip | |
Fixed assertion typos
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/site_lut_mapping_cache.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga_interchange/site_lut_mapping_cache.cc b/fpga_interchange/site_lut_mapping_cache.cc index 3796d7ab..86f39f2c 100644 --- a/fpga_interchange/site_lut_mapping_cache.cc +++ b/fpga_interchange/site_lut_mapping_cache.cc @@ -127,8 +127,8 @@ bool SiteLutMappingResult::apply (const SiteInformation& siteInfo) { NPNR_ASSERT(cellInfo); // Double check BEL binding - NPNR_ASSERT(cellInfo->bel.tile = siteInfo.tile); - NPNR_ASSERT(cellInfo->bel.index = cell.belIndex); + NPNR_ASSERT(cellInfo->bel.tile == siteInfo.tile); + NPNR_ASSERT(cellInfo->bel.index == cell.belIndex); // Cell <-> BEL pin map size_t numPins = cellInfo->lut_cell.pins.size(); |