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| author | David Shah <davey1576@gmail.com> | 2018-11-15 11:26:08 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-11-15 11:26:08 +0000 |
| commit | 9472b6d78f68544d430feeae6d75dbd2dc43019d (patch) | |
| tree | 0ab6b20c90d4a93cd9e2d0c14bdadb296e159cdc /generic/arch.cc | |
| parent | d3b2065cd7d2470a132c055f4bd88d270e1e8fe1 (diff) | |
| parent | 9f9b242cf0a3b587df8f5b0eb542ca7256ca0eb9 (diff) | |
| download | nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.tar.gz nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.tar.bz2 nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.zip | |
Merge pull request #103 from YosysHQ/timingapi
Timing constraints API, multiple clock domains
Diffstat (limited to 'generic/arch.cc')
| -rw-r--r-- | generic/arch.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/generic/arch.cc b/generic/arch.cc index 4f2e07a2..77417d27 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -463,11 +463,16 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort } // Get the port class, also setting clockPort if applicable -TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const +TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const { return TMG_IGNORE; } +TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const +{ + NPNR_ASSERT_FALSE("no clocking info for generic"); +} + bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } bool Arch::isBelLocationValid(BelId bel) const { return true; } |