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authorDavid Shah <dave@ds0.me>2021-02-05 11:32:09 +0000
committerGitHub <noreply@github.com>2021-02-05 11:32:09 +0000
commitb0f9b7834e4cb035d1fd60f0fa1948c0fdfa233c (patch)
treed8b70c19580030a1ee28431b5d2287a0ae1690da /generic/arch.cc
parent40d026e6fc5ab94c732682c62a6803bd3140953e (diff)
parent450bfae86cc807e4aec8d3b725169fd044212079 (diff)
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Merge pull request #570 from litghost/make_id_string_list_explicit
Mark IdString and IdStringList single argument constructors explicit.
Diffstat (limited to 'generic/arch.cc')
-rw-r--r--generic/arch.cc13
1 files changed, 5 insertions, 8 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index 9b131959..912f8a53 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -216,12 +216,9 @@ void Arch::setDelayScaling(double scale, double offset)
args.delayOffset = offset;
}
-void Arch::addCellTimingClock(IdStringList cell, IdString port)
-{
- cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT;
-}
+void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
-void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay)
+void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
{
if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
@@ -230,7 +227,7 @@ void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toP
cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
}
-void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
+void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
{
TimingClockingInfo ci;
ci.clock_port = clock;
@@ -241,7 +238,7 @@ void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clo
cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
}
-void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq)
+void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
{
TimingClockingInfo ci;
ci.clock_port = clock;
@@ -256,7 +253,7 @@ void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString cl
Arch::Arch(ArchArgs args) : chipName("generic"), args(args)
{
// Dummy for empty decals
- decal_graphics[IdString()];
+ decal_graphics[DecalId()];
}
void IdString::initialize_arch(const BaseCtx *ctx) {}