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authorDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
committerDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
commitbf42e525cb7ab6ae071b16dfeca55194878be69c (patch)
treec9282e371fc57a71550e1dcca0ae9e38724d5bf4 /generic/arch.cc
parenta0994d515454a696c98602980b298ee61aa03f4e (diff)
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Arch API: New specification for timing port classes
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'generic/arch.cc')
-rw-r--r--generic/arch.cc8
1 files changed, 5 insertions, 3 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index 0fa93da8..25e4d08c 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -435,9 +435,11 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return false;
}
-IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); }
-
-bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
+// Get the port class, also setting clockPort if applicable
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
+{
+ return TMG_IGNORE;
+}
bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
bool Arch::isBelLocationValid(BelId bel) const { return true; }