Merge branch 'master' into 'master'

Master

See merge request eddiehung/nextpnr!7

1 files changed, 14 insertions, 7 deletions

diff --git a/generic/arch.h b/generic/arch.h
index e1516569..61e6b033 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -43,6 +43,7 @@ struct WireInfo
     std::vector<PipId> downhill, uphill, aliases;
     BelPin uphill_bel_pin;
     std::vector<BelPin> downhill_bel_pins;
+    std::vector<BelPin> bel_pins;
     DecalXY decalxy;
     int x, y;
 };
@@ -83,21 +84,23 @@ struct Arch : BaseCtx
     std::unordered_map<GroupId, GroupInfo> groups;
 
     std::vector<IdString> bel_ids, wire_ids, pip_ids;
-    std::unordered_map<IdString, std::vector<IdString>> bel_ids_by_type;
 
     std::unordered_map<Loc, BelId> bel_by_loc;
-    std::unordered_map<int, std::unordered_map<int, std::vector<BelId>>> bels_by_tile;
+    std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
 
     std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
     DecalXY frame_decalxy;
 
+    int gridDimX, gridDimY;
+    std::vector<std::vector<int>> tileDimZ;
+
     float grid_distance_to_delay;
 
     void addWire(IdString name, int x, int y);
     void addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
     void addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
 
-    void addBel(IdString name, IdString type, int x, int y, int z, bool gb);
+    void addBel(IdString name, IdString type, Loc loc, bool gb);
     void addBelInput(IdString bel, IdString name, IdString wire);
     void addBelOutput(IdString bel, IdString name, IdString wire);
     void addBelInout(IdString bel, IdString name, IdString wire);
@@ -130,6 +133,10 @@ struct Arch : BaseCtx
     BelType belTypeFromId(IdString id) const { return id; }
     PortPin portPinFromId(IdString id) const { return id; }
 
+    int getGridDimX() const { return gridDimX; }
+    int getGridDimY() const { return gridDimY; }
+    int getTileDimZ(int x, int y) const { return tileDimZ[x][y]; }
+
     BelId getBelByName(IdString name) const;
     IdString getBelName(BelId bel) const;
     Loc getBelLocation(BelId bel) const;
@@ -143,11 +150,10 @@ struct Arch : BaseCtx
     IdString getBoundBelCell(BelId bel) const;
     IdString getConflictingBelCell(BelId bel) const;
     const std::vector<BelId> &getBels() const;
-    const std::vector<BelId> &getBelsByType(BelType type) const;
     BelType getBelType(BelId bel) const;
-    WireId getWireBelPin(BelId bel, PortPin pin) const;
-    BelPin getBelPinUphill(WireId wire) const;
-    const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const;
+    WireId getBelPinWire(BelId bel, PortPin pin) const;
+    PortType getBelPinType(BelId bel, PortPin pin) const;
+    std::vector<PortPin> getBelPins(BelId bel) const;
 
     WireId getWireByName(IdString name) const;
     IdString getWireName(WireId wire) const;
@@ -159,6 +165,7 @@ struct Arch : BaseCtx
     IdString getConflictingWireNet(WireId wire) const;
     DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
     const std::vector<WireId> &getWires() const;
+    const std::vector<BelPin> &getWireBelPins(WireId wire) const;
 
     PipId getPipByName(IdString name) const;
     IdString getPipName(PipId pip) const;