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authorDavid Shah <davey1576@gmail.com>2018-08-08 19:23:47 +0200
committerGitHub <noreply@github.com>2018-08-08 19:23:47 +0200
commitcd4e761bb799ca99f02d3aa177961af28a93f2d8 (patch)
treea6424fb4ea70b868efb1375bb9cf3db992e3059c /generic/arch.h
parent2390f7f59c05870845da349536cb384964cdb874 (diff)
parent751335977fe7d69b23f6110ec4938408ec7a7ff8 (diff)
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Merge pull request #44 from YosysHQ/improve_timing_spec
Speed up budget allocator using topographical ordering and update cell timing API
Diffstat (limited to 'generic/arch.h')
-rw-r--r--generic/arch.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/generic/arch.h b/generic/arch.h
index 0e0aec27..c5863ec3 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -215,8 +215,8 @@ struct Arch : BaseCtx
DecalXY getGroupDecal(GroupId group) const;
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
- IdString getPortClock(const CellInfo *cell, IdString port) const;
- bool isClockPort(const CellInfo *cell, IdString port) const;
+ // Get the port class, also setting clockPort if applicable
+ TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const;
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
bool isBelLocationValid(BelId bel) const;