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authorMiodrag Milanovic <mmicko@gmail.com>2020-07-25 10:17:13 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2020-07-25 10:17:13 +0200
commitfe398ab983aee9283f61c288dc98d94542c30332 (patch)
tree3349c93ac87f5758009c53b3e2eb5b9a130cd0d6 /generic/arch_pybindings.cc
parentbb6e6a15f1f1a061f4b59c3eddd3430d57681c6d (diff)
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Diffstat (limited to 'generic/arch_pybindings.cc')
-rw-r--r--generic/arch_pybindings.cc52
1 files changed, 26 insertions, 26 deletions
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 325f4153..c00686dd 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -157,29 +157,29 @@ void arch_wrap_python(py::module &m)
fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>,
conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire",
"name"_a, "type"_a, "x"_a,
- "y"_a);
+ "y"_a);
fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>,
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
- pass_through<Loc>>::def_wrap(ctx_cls, "addPip",
- "name"_a, "type"_a, "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
+ pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
+ "delay"_a, "loc"_a);
fn_wrapper_5a_v<Context, decltype(&Context::addAlias), &Context::addAlias, conv_from_str<IdString>,
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
- pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias",
- "name"_a, "type"_a, "srcWire"_a, "dstWire"_a, "delay"_a);
+ pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias", "name"_a, "type"_a, "srcWire"_a,
+ "dstWire"_a, "delay"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
"name"_a, "type"_a,
- "loc"_a, "gb"_a);
+ "loc"_a, "gb"_a);
fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>,
- conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput",
- "bel"_a, "name"_a, "wire"_a);
+ conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
+ "name"_a, "wire"_a);
fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>,
- conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput",
- "bel"_a, "name"_a, "wire"_a);
+ conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
+ "name"_a, "wire"_a);
fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>,
- conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout",
- "bel"_a, "name"_a, "wire"_a);
+ conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
+ "name"_a, "wire"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>,
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
@@ -202,14 +202,14 @@ void arch_wrap_python(py::module &m)
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", "group"_a, "decalxy"_a);
fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr",
- "wire"_a, "key"_a, "value"_a);
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", "wire"_a,
+ "key"_a, "value"_a);
fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr",
- "bel"_a, "key"_a, "value"_a);
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", "bel"_a,
+ "key"_a, "value"_a);
fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr",
- "pip"_a, "key"_a, "value"_a);
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", "pip"_a,
+ "key"_a, "value"_a);
fn_wrapper_1a_v<Context, decltype(&Context::setLutK), &Context::setLutK, pass_through<int>>::def_wrap(
ctx_cls, "setLutK", "K"_a);
@@ -217,20 +217,20 @@ void arch_wrap_python(py::module &m)
pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", "scale"_a, "offset"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock,
- conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock",
- "cell"_a, "port"_a);
+ conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", "cell"_a,
+ "port"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay,
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
- pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay",
- "cell"_a, "fromPort"_a, "toPort"_a, "delay"_a);
+ pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay", "cell"_a, "fromPort"_a,
+ "toPort"_a, "delay"_a);
fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold,
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
- pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold",
- "cell"_a, "port"_a, "clock"_a, "setup"_a, "hold"_a);
+ pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", "cell"_a, "port"_a, "clock"_a,
+ "setup"_a, "hold"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut,
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
- pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut",
- "cell"_a, "port"_a, "clock"_a, "clktoq"_a);
+ pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut", "cell"_a, "port"_a,
+ "clock"_a, "clktoq"_a);
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 03:50:17 +0000