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author | David Shah <davey1576@gmail.com> | 2019-04-19 17:40:55 +0100 |
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committer | GitHub <noreply@github.com> | 2019-04-19 17:40:55 +0100 |
commit | 5344bc3b65f4e06f983db781e9a82d30b3f1512b (patch) | |
tree | 5f794074ccc963a9dbf756558e34a8eba0d5fa26 /generic/examples/README.md | |
parent | 0be844e6a8d0a36a50815ec5331fd7480dd20db6 (diff) | |
parent | 87a24460813b9f52189323352554a1c352836ee2 (diff) | |
download | nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.tar.gz nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.tar.bz2 nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.zip |
Merge pull request #261 from YosysHQ/pygeneric
Python API for generic architecture
Diffstat (limited to 'generic/examples/README.md')
-rw-r--r-- | generic/examples/README.md | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/generic/examples/README.md b/generic/examples/README.md new file mode 100644 index 00000000..9fd106d9 --- /dev/null +++ b/generic/examples/README.md @@ -0,0 +1,14 @@ +# Generic Architecture Example + +This contains a simple, artificial, example of the nextpnr generic API. + + - simple.py procedurally generates a simple FPGA architecture with IO at the edges, + logic slices in all other tiles, and interconnect only between adjacent tiles + + - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) + + - write_fasm.py uses the nextpnr Python API to write a FASM file for a design + + - bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design + + - Run simple.sh to build an example design on the FPGA above
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