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authorDavid Shah <davey1576@gmail.com>2019-04-19 17:40:55 +0100
committerGitHub <noreply@github.com>2019-04-19 17:40:55 +0100
commit5344bc3b65f4e06f983db781e9a82d30b3f1512b (patch)
tree5f794074ccc963a9dbf756558e34a8eba0d5fa26 /generic/examples/simple_config.py
parent0be844e6a8d0a36a50815ec5331fd7480dd20db6 (diff)
parent87a24460813b9f52189323352554a1c352836ee2 (diff)
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Merge pull request #261 from YosysHQ/pygeneric
Python API for generic architecture
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diff --git a/generic/examples/simple_config.py b/generic/examples/simple_config.py
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+# Grid size including IOBs at edges
+X = 12
+Y = 12
+# SLICEs per tile
+N = 8
+# LUT input count
+K = 4
+# Number of local wires
+Wl = N*(K+1) + 8
+# 1/Fc for bel input wire pips
+Si = 4
+# 1/Fc for Q to local wire pips
+Sq = 4
+# ~1/Fc local to neighbour local wire pips
+Sl = 8 \ No newline at end of file