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| author | David Shah <dave@ds0.me> | 2019-11-08 16:28:39 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-08 16:28:39 +0000 |
| commit | 6a335411da6eb54f0960eb514c5384e4ae60c3a7 (patch) | |
| tree | 0ff3e83dc88a2b59275136e098ba5e59ed473480 /generic/examples/simple_timing.py | |
| parent | caf7abdb8dd7ec97801fd13efc8ae132e637ecd3 (diff) | |
| parent | a4848f6902f81b6d3f2a36ab853922047e177288 (diff) | |
| download | nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.tar.gz nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.tar.bz2 nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.zip | |
Merge pull request #350 from pepijndevos/newslice
Dedicated output for LUT in GENERIC_SLICE
Diffstat (limited to 'generic/examples/simple_timing.py')
| -rw-r--r-- | generic/examples/simple_timing.py | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py index 2ccb197e..1067b556 100644 --- a/generic/examples/simple_timing.py +++ b/generic/examples/simple_timing.py @@ -1,15 +1,13 @@ for cname, cell in ctx.cells: - if cell.type != "GENERIC_SLICE": - continue - if cname in ("$PACKER_GND", "$PACKER_VCC"): - continue - K = int(cell.params["K"]) - if int(cell.params["FF_USED"], 2) == 1: - ctx.addCellTimingClock(cell=cname, port="CLK") - for i in range(K): - ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", - setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) - ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) - else: - for i in range(K): - ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2))
\ No newline at end of file + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2)) |