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| author | gatecat <gatecat@ds0.me> | 2021-02-17 10:16:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-17 10:16:45 +0000 |
| commit | da1ecf0813cb07a65bc1ca498d0f9c896cc3a675 (patch) | |
| tree | 5b9625b3852b79acb73ae55cd39078b18ab29019 /generic/pack.cc | |
| parent | a77ceec5cf5603542d87724d9fdc51d48fa29327 (diff) | |
| parent | 26a187e5ebcd1bdb6e079a91e25b610dc603aab2 (diff) | |
| download | nextpnr-da1ecf0813cb07a65bc1ca498d0f9c896cc3a675.tar.gz nextpnr-da1ecf0813cb07a65bc1ca498d0f9c896cc3a675.tar.bz2 nextpnr-da1ecf0813cb07a65bc1ca498d0f9c896cc3a675.zip | |
Merge pull request #586 from litghost/add_cell_bel_mapping_only
Add Cell -> BEL Pin maps to FPGA interchange arch.
Diffstat (limited to 'generic/pack.cc')
0 files changed, 0 insertions, 0 deletions