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authorPepijn de Vos <pepijndevos@gmail.com>2019-11-08 15:54:27 +0100
committerPepijn de Vos <pepijndevos@gmail.com>2019-11-08 15:54:27 +0100
commit7c362f292c0807b1e781922c79af94fd8b82477c (patch)
tree81d3f60003b967c46804f23a677fab7a5f25aaa8 /generic/synth/prims.v
parent21c09c8b8f5e0456cc4d7e8017c27d25dd676377 (diff)
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dedicated output for LUT in GENERIC_SLICE
Diffstat (limited to 'generic/synth/prims.v')
-rw-r--r--generic/synth/prims.v16
1 files changed, 7 insertions, 9 deletions
diff --git a/generic/synth/prims.v b/generic/synth/prims.v
index 95fcfac7..47a5df0f 100644
--- a/generic/synth/prims.v
+++ b/generic/synth/prims.v
@@ -21,21 +21,19 @@ endmodule
module GENERIC_SLICE #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0,
- parameter FF_USED = 1'b0
) (
input CLK,
input [K-1:0] I,
+ output F,
output Q
);
+ wire f_wire;
- wire lut_q;
- LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q));
+ LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
- generate if (FF_USED)
- DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q));
- else
- assign Q = lut_q;
- endgenerate
+ DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
+
+ assign F = f_wire;
endmodule
module GENERIC_IOB #(
@@ -56,4 +54,4 @@ module GENERIC_IOB #(
generate if (INPUT_USED)
assign O = PAD;
endgenerate
-endmodule \ No newline at end of file
+endmodule