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authorgatecat <gatecat@ds0.me>2021-12-30 13:18:34 +0000
committergatecat <gatecat@ds0.me>2022-01-04 20:19:29 +0000
commite88bd34c02272ecdad6295123941d9040fa4f043 (patch)
tree2ff879a3a856d19f61cc0c0875e7a3aa7fba7ac1 /generic/viaduct/example/example_prims.v
parent089ca8258e6f4dc93f8d39594c1109a8578cdc98 (diff)
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Viaduct API for a hybrid between generic and full-custom arch
Signed-off-by: gatecat <gatecat@ds0.me>
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diff --git a/generic/viaduct/example/example_prims.v b/generic/viaduct/example/example_prims.v
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+module LUT4 #(
+ parameter [15:0] INIT = 0
+) (
+ input [3:0] I,
+ output F
+);
+ wire [7:0] s3 = I[3] ? INIT[15:8] : INIT[7:0];
+ wire [3:0] s2 = I[2] ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = I[1] ? s2[ 3:2] : s2[1:0];
+ assign F = I[0] ? s1[1] : s1[0];
+endmodule
+
+module DFF (
+ input CLK, D,
+ output reg Q
+);
+ initial Q = 1'b0;
+ always @(posedge CLK)
+ Q <= D;
+endmodule
+
+module INBUF (
+ input PAD,
+ output O,
+);
+ assign O = PAD;
+endmodule
+
+module OUTBUF (
+ output PAD,
+ input I,
+);
+ assign PAD = I;
+endmodule
+