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| author | David Shah <dave@ds0.me> | 2018-11-04 14:58:25 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2018-11-12 14:03:58 +0000 |
| commit | dab70466cdce724611904e066197feef564f3eea (patch) | |
| tree | d627f399b6784fd1d26dcb7f874f885bc7b3d1a6 /generic | |
| parent | 8af86ff37d3f370f2bf9add46261f3b5a6b3f5a4 (diff) | |
| download | nextpnr-dab70466cdce724611904e066197feef564f3eea.tar.gz nextpnr-dab70466cdce724611904e066197feef564f3eea.tar.bz2 nextpnr-dab70466cdce724611904e066197feef564f3eea.zip | |
generic: Update arch to new timing API
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic')
| -rw-r--r-- | generic/arch.cc | 7 | ||||
| -rw-r--r-- | generic/arch.h | 14 |
2 files changed, 18 insertions, 3 deletions
diff --git a/generic/arch.cc b/generic/arch.cc index 3e95159a..4439f517 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -461,11 +461,16 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort } // Get the port class, also setting clockPort if applicable -TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const +TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const { return TMG_IGNORE; } +TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const +{ + NPNR_ASSERT_FALSE("no clocking info for generic"); +} + bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } bool Arch::isBelLocationValid(BelId bel) const { return true; } diff --git a/generic/arch.h b/generic/arch.h index 22966e2a..1eca9701 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -209,6 +209,14 @@ struct Arch : BaseCtx delay_t getDelayEpsilon() const { return 0.01; } delay_t getRipupDelayPenalty() const { return 1.0; } float getDelayNS(delay_t v) const { return v; } + + DelayInfo getDelayFromNS(float ns) const + { + DelayInfo del; + del.delay = ns; + return del; + } + uint32_t getDelayChecksum(delay_t v) const { return 0; } bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const; @@ -223,8 +231,10 @@ struct Arch : BaseCtx DecalXY getGroupDecal(GroupId group) const; bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; - // Get the port class, also setting clockPort if applicable - TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const; + // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const; + // Get the TimingClockingInfo of a port + TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const; bool isValidBelForCell(CellInfo *cell, BelId bel) const; bool isBelLocationValid(BelId bel) const; |