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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-07-05 19:43:24 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2022-07-05 19:43:24 +1000 |
| commit | 3364a3b6746c6df62a36e1dd319afaa97259d6ad (patch) | |
| tree | fe7e96804ecee6f46ffef4522a1a3bba290fd86a /gowin/cells.h | |
| parent | 5d915a550ba8a825fa29a2cab3851adea20f40fb (diff) | |
| parent | 86396c41d64d2583ec1dffca4298e83d927f0762 (diff) | |
| download | nextpnr-3364a3b6746c6df62a36e1dd319afaa97259d6ad.tar.gz nextpnr-3364a3b6746c6df62a36e1dd319afaa97259d6ad.tar.bz2 nextpnr-3364a3b6746c6df62a36e1dd319afaa97259d6ad.zip | |
Merge branch 'master' into clock-wip
Diffstat (limited to 'gowin/cells.h')
| -rw-r--r-- | gowin/cells.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gowin/cells.h b/gowin/cells.h index 8f0636b8..b6d86497 100644 --- a/gowin/cells.h +++ b/gowin/cells.h @@ -111,6 +111,8 @@ inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SLICE; } +inline bool is_sram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_RAM16SDP4; } + // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports // as needed. Set no_dff if a DFF is not being used, so that the output // can be reconnected @@ -125,6 +127,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l // Convert a Gowin IO buffer to a IOB bel void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells); +// Convert RAM16 to write port +void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw); + +// Convert RAM16 to slice +void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index); + NEXTPNR_NAMESPACE_END #endif |