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authorYRabbit <rabbit@yrabbit.cyou>2022-12-30 11:55:39 +1000
committerYRabbit <rabbit@yrabbit.cyou>2022-12-30 11:55:39 +1000
commitb8ab3116b223648af19c190c392c1fe36844907b (patch)
tree6226d4a8605d8b99ff1e629d4d9dae0eb6b9e7c0 /gowin/globals.h
parent8424dc79d2555ce6b070371c9a5fb11aa76e950d (diff)
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gowin: improve clock wire routing
The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/globals.h')
-rw-r--r--gowin/globals.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/gowin/globals.h b/gowin/globals.h
index 69232d7c..307a1a2c 100644
--- a/gowin/globals.h
+++ b/gowin/globals.h
@@ -39,32 +39,32 @@ class GowinGlobalRouter
{
IdString name;
int clock_ports;
- BelId clock_io_bel;
- WireId clock_io_wire; // IO wire if there is one
- int clock; // clock #
+ BelId clock_bel;
+ WireId clock_wire; // clock wire if there is one
+ int clock; // clock #
globalnet_t()
{
name = IdString();
clock_ports = 0;
- clock_io_bel = BelId();
- clock_io_wire = WireId();
+ clock_bel = BelId();
+ clock_wire = WireId();
clock = -1;
}
globalnet_t(IdString _name)
{
name = _name;
clock_ports = 0;
- clock_io_bel = BelId();
- clock_io_wire = WireId();
+ clock_bel = BelId();
+ clock_wire = WireId();
clock = -1;
}
// sort
bool operator<(const globalnet_t &other) const
{
- if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
- return !(clock_io_wire != WireId());
+ if ((clock_wire != WireId()) ^ (other.clock_wire != WireId())) {
+ return !(clock_wire != WireId());
}
return clock_ports < other.clock_ports;
}
@@ -76,7 +76,7 @@ class GowinGlobalRouter
std::vector<globalnet_t> nets;
bool is_clock_port(PortRef const &user);
- std::pair<WireId, BelId> clock_io(Context *ctx, PortRef const &driver);
+ std::pair<WireId, BelId> clock_src(Context *ctx, PortRef const &driver);
void gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets);
IdString route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock, pool<IdString> &used_pips,
pool<IdString> &undo_wires);