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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-12-04 15:06:44 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2022-12-04 15:06:44 +1000 |
| commit | 2e68962a025999ec85276f6362540c13ccfcd752 (patch) | |
| tree | e1c0d9538a33bce405a5d14ca67baa6ccd1297b9 /gowin/pack.cc | |
| parent | f07d9a18356ec8df74d9c42693f7b9307e390a7f (diff) | |
| download | nextpnr-2e68962a025999ec85276f6362540c13ccfcd752.tar.gz nextpnr-2e68962a025999ec85276f6362540c13ccfcd752.tar.bz2 nextpnr-2e68962a025999ec85276f6362540c13ccfcd752.zip | |
gowin: add PLL pins processing
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/pack.cc')
| -rw-r--r-- | gowin/pack.cc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/gowin/pack.cc b/gowin/pack.cc index 1e0380c1..c36a4757 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -820,8 +820,6 @@ static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell) } } -static bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); } - // Pack IO logic static void pack_iologic(Context *ctx) { @@ -1021,10 +1019,11 @@ static void pack_plls(Context *ctx) if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") { // Unused ports will be disabled during image generation. Here we add flags for such ports. Property pr_enable("ENABLE"), pr_disable("DISABLE"); - IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS}, {id_CLKOUTD, id_CLKOUTDIV}, - {id_CLKOUTD3, id_CLKOUTDIV3}, {id_LOCK, id_FLOCK}, - {id_RESET_P, id_PWDEN}, {id_RESET, id_RSTEN}}; - for (int i = 0; i < 6; ++i) { + IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS}, + {id_CLKOUTD, id_CLKOUTDIV}, + {id_CLKOUTD3, id_CLKOUTDIV3}, + {id_LOCK, id_FLOCK}}; + for (int i = 0; i < 4; ++i) { ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable); } // B half |