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| author | YRabbit <rabbit@yrabbit.cyou> | 2023-01-30 12:49:57 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2023-01-30 12:49:57 +1000 |
| commit | 6a1212a1e14d19bda114317e9f544b534cbf2841 (patch) | |
| tree | 2c74bf137a3972c52986c7af6a8f4753fd1d5e05 /gowin/pack.cc | |
| parent | f80b871dd54b5215480a8eb00313a7ac16d9e883 (diff) | |
| download | nextpnr-6a1212a1e14d19bda114317e9f544b534cbf2841.tar.gz nextpnr-6a1212a1e14d19bda114317e9f544b534cbf2841.tar.bz2 nextpnr-6a1212a1e14d19bda114317e9f544b534cbf2841.zip | |
gowin: Add PLL support for the GW1NR-9 chip
And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/pack.cc')
| -rw-r--r-- | gowin/pack.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gowin/pack.cc b/gowin/pack.cc index cb24ac02..09e5c880 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -1043,7 +1043,8 @@ static void pack_plls(Context *ctx) switch (ci->type.hash()) { case ID_rPLL: { - if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C") { + if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C" || + parm_device == "GW1NR-9") { pll_disable_unused_ports(ctx, ci); // A cell std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_rPLL, ci->name.str(ctx) + "$rpll"); |