Revert "Introduce proxies for locked access to ctx"

This reverts commit 89809a8b810dd57f50f365d70a0ce547705f8dbb.

1 files changed, 37 insertions, 38 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index cb7c44b8..c9dd26c5 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -3,7 +3,6 @@
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@symbioticeda.com>
  *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
- *  Copyright (C) 2018  Serge Bazanski  <q3k@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -25,44 +24,44 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-bool ArchRProxyMethods::logicCellsCompatible(const std::vector<const CellInfo *> &cells) const
+bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) const
 {
     bool dffs_exist = false, dffs_neg = false;
     const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
     int locals_count = 0;
 
     for (auto cell : cells) {
-        if (bool_or_default(cell->params, parent_->id_dff_en)) {
+        if (bool_or_default(cell->params, id_dff_en)) {
             if (!dffs_exist) {
                 dffs_exist = true;
-                cen = get_net_or_empty(cell, parent_->id_cen);
-                clk = get_net_or_empty(cell, parent_->id_clk);
-                sr = get_net_or_empty(cell, parent_->id_sr);
+                cen = get_net_or_empty(cell, id_cen);
+                clk = get_net_or_empty(cell, id_clk);
+                sr = get_net_or_empty(cell, id_sr);
 
-                if (!parent_->isGlobalNet(cen) && cen != nullptr)
+                if (!isGlobalNet(cen) && cen != nullptr)
                     locals_count++;
-                if (!parent_->isGlobalNet(clk) && clk != nullptr)
+                if (!isGlobalNet(clk) && clk != nullptr)
                     locals_count++;
-                if (!parent_->isGlobalNet(sr) && sr != nullptr)
+                if (!isGlobalNet(sr) && sr != nullptr)
                     locals_count++;
 
-                if (bool_or_default(cell->params, parent_->id_neg_clk)) {
+                if (bool_or_default(cell->params, id_neg_clk)) {
                     dffs_neg = true;
                 }
             } else {
-                if (cen != get_net_or_empty(cell, parent_->id_cen))
+                if (cen != get_net_or_empty(cell, id_cen))
                     return false;
-                if (clk != get_net_or_empty(cell, parent_->id_clk))
+                if (clk != get_net_or_empty(cell, id_clk))
                     return false;
-                if (sr != get_net_or_empty(cell, parent_->id_sr))
+                if (sr != get_net_or_empty(cell, id_sr))
                     return false;
-                if (dffs_neg != bool_or_default(cell->params, parent_->id_neg_clk))
+                if (dffs_neg != bool_or_default(cell->params, id_neg_clk))
                     return false;
             }
         }
 
-        const NetInfo *i0 = get_net_or_empty(cell, parent_->id_i0), *i1 = get_net_or_empty(cell, parent_->id_i1),
-                      *i2 = get_net_or_empty(cell, parent_->id_i2), *i3 = get_net_or_empty(cell, parent_->id_i3);
+        const NetInfo *i0 = get_net_or_empty(cell, id_i0), *i1 = get_net_or_empty(cell, id_i1),
+                      *i2 = get_net_or_empty(cell, id_i2), *i3 = get_net_or_empty(cell, id_i3);
         if (i0 != nullptr)
             locals_count++;
         if (i1 != nullptr)
@@ -76,57 +75,57 @@ bool ArchRProxyMethods::logicCellsCompatible(const std::vector<const CellInfo *>
     return locals_count <= 32;
 }
 
-bool ArchRProxyMethods::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel) const
 {
-    if (parent_->getBelType(bel) == TYPE_ICESTORM_LC) {
+    if (getBelType(bel) == TYPE_ICESTORM_LC) {
         std::vector<const CellInfo *> bel_cells;
-        for (auto bel_other : parent_->getBelsAtSameTile(bel)) {
-            IdString cell_other = getBoundBelCell(bel_other);
+        for (auto bel_other : getBelsAtSameTile(bel)) {
+            IdString cell_other = getBoundBelCellUnlocked(bel_other);
             if (cell_other != IdString()) {
-                const CellInfo *ci_other = parent_->cells.at(cell_other).get();
+                const CellInfo *ci_other = cells.at(cell_other).get();
                 bel_cells.push_back(ci_other);
             }
         }
         return logicCellsCompatible(bel_cells);
     } else {
-        IdString cellId = getBoundBelCell(bel);
+        IdString cellId = getBoundBelCellUnlocked(bel);
         if (cellId == IdString())
             return true;
         else
-            return isValidBelForCell(parent_->cells.at(cellId).get(), bel);
+            return isValidBelForCell(cells.at(cellId).get(), bel);
     }
 }
 
-bool ArchRProxyMethods::isValidBelForCell(CellInfo *cell, BelId bel) const
+bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
 {
-    if (cell->type == parent_->id_icestorm_lc) {
-        NPNR_ASSERT(parent_->getBelType(bel) == TYPE_ICESTORM_LC);
+    if (cell->type == id_icestorm_lc) {
+        NPNR_ASSERT(getBelType(bel) == TYPE_ICESTORM_LC);
 
         std::vector<const CellInfo *> bel_cells;
 
-        for (auto bel_other : parent_->getBelsAtSameTile(bel)) {
-            IdString cell_other = getBoundBelCell(bel_other);
+        for (auto bel_other : getBelsAtSameTile(bel)) {
+            IdString cell_other = getBoundBelCellUnlocked(bel_other);
             if (cell_other != IdString() && bel_other != bel) {
-                const CellInfo *ci_other = parent_->cells.at(cell_other).get();
+                const CellInfo *ci_other = cells.at(cell_other).get();
                 bel_cells.push_back(ci_other);
             }
         }
 
         bel_cells.push_back(cell);
         return logicCellsCompatible(bel_cells);
-    } else if (cell->type == parent_->id_sb_io) {
-        return parent_->getBelPackagePin(bel) != "";
-    } else if (cell->type == parent_->id_sb_gb) {
+    } else if (cell->type == id_sb_io) {
+        return getBelPackagePin(bel) != "";
+    } else if (cell->type == id_sb_gb) {
         bool is_reset = false, is_cen = false;
-        NPNR_ASSERT(cell->ports.at(parent_->id_glb_buf_out).net != nullptr);
-        for (auto user : cell->ports.at(parent_->id_glb_buf_out).net->users) {
-            if (is_reset_port(parent_, user))
+        NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
+        for (auto user : cell->ports.at(id_glb_buf_out).net->users) {
+            if (is_reset_port(this, user))
                 is_reset = true;
-            if (is_enable_port(parent_, user))
+            if (is_enable_port(this, user))
                 is_cen = true;
         }
-        IdString glb_net = parent_->getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
-        int glb_id = std::stoi(std::string("") + glb_net.str(parent_).back());
+        IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
+        int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
         if (is_reset && is_cen)
             return false;
         else if (is_reset)