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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-17 15:39:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-17 15:39:19 +0200 |
| commit | f38c5660cbc85baa48bb8b16d3877269d66c8bd5 (patch) | |
| tree | e9cf3a9583326b1123531b36d7630db0e82a6b80 /ice40/bitstream.cc | |
| parent | a4ad3533fe73d279743ba72e6e7cb01be3dc0d03 (diff) | |
| download | nextpnr-f38c5660cbc85baa48bb8b16d3877269d66c8bd5.tar.gz nextpnr-f38c5660cbc85baa48bb8b16d3877269d66c8bd5.tar.bz2 nextpnr-f38c5660cbc85baa48bb8b16d3877269d66c8bd5.zip | |
Move BitstreamInfoPOD to ice40 chipdb blob
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/bitstream.cc')
| -rw-r--r-- | ice40/bitstream.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 2913303c..997ef7d9 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -155,7 +155,7 @@ void write_asc(const Design &design, std::ostream &out) const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; if (cell.second->type == "ICESTORM_LC") { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT"); bool neg_clk = get_param_or_def(cell.second, "NEG_CLK"); bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE"); @@ -181,7 +181,7 @@ void write_asc(const Design &design, std::ostream &out) lc.at(i), i); set_config(ti, config.at(y).at(x), "NegClk", neg_clk); } else if (cell.second->type == "SB_IO") { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE"); bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER"); bool pullup = get_param_or_def(cell.second, "PULLUP"); @@ -254,7 +254,7 @@ void write_asc(const Design &design, std::ostream &out) for (auto bel : chip.getBels()) { if (chip.bel_to_cell[bel.index] == IdString() && chip.getBelType(bel) == TYPE_SB_IO) { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; auto ieren = get_ieren(bi, x, y, z); @@ -273,7 +273,7 @@ void write_asc(const Design &design, std::ostream &out) chip.getBelType(bel) == TYPE_ICESTORM_RAM) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y; - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; if ((chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K)) { set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); @@ -285,7 +285,7 @@ void write_asc(const Design &design, std::ostream &out) for (int y = 0; y < ci.height; y++) { for (int x = 0; x < ci.width; x++) { TileType tile = tile_at(chip, x, y); - TileInfoPOD &ti = bi.tiles_nonrouting[tile]; + const TileInfoPOD &ti = bi.tiles_nonrouting[tile]; // set all ColBufCtrl bits (FIXME) bool setColBufCtrl = true; |