CarryInSet added to bitstream gen, add counter tb

Signed-off-by: David Shah <davey1576@gmail.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/ice40/carry_tests/counter_tb.v b/ice40/carry_tests/counter_tb.v
new file mode 100644
index 00000000..ede133a7
--- /dev/null
+++ b/ice40/carry_tests/counter_tb.v
@@ -0,0 +1,23 @@
+module counter_tb;
+    reg clk;
+    always #5 clk = (clk === 1'b0);
+
+    wire outa, outb, outc, outd;
+
+    chip uut (
+        .clk(clk),
+        .cen(1'b1),
+        .rst(1'b0),
+        .outa(outa),
+        .outb(outb),
+        .outc(outc),
+	.outd(outd)
+    );
+
+    initial begin
+        $dumpfile("counter_tb.vcd");
+        $dumpvars(0, counter_tb);
+        repeat (100000) @(posedge clk);
+        $finish;
+    end
+endmodule