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authorDavid Shah <davey1576@gmail.com>2018-06-26 13:08:28 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-26 13:08:28 +0200
commitded9df61dc1ce390a6751c214c02a2acb3a57577 (patch)
tree050aef4232cf7f4f3b075943956ba2dbe1bdf10c /ice40/carry_tests
parente51dd15b6bca1bb9e01b5275e68036a658f6c504 (diff)
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Working on debugging carry packer
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/carry_tests')
-rw-r--r--ice40/carry_tests/.gitignore2
-rw-r--r--ice40/carry_tests/counter.v9
-rw-r--r--ice40/carry_tests/test.pcf10
-rwxr-xr-xice40/carry_tests/test.sh16
4 files changed, 37 insertions, 0 deletions
diff --git a/ice40/carry_tests/.gitignore b/ice40/carry_tests/.gitignore
new file mode 100644
index 00000000..749cb303
--- /dev/null
+++ b/ice40/carry_tests/.gitignore
@@ -0,0 +1,2 @@
+*.vcd
+*_out.v
diff --git a/ice40/carry_tests/counter.v b/ice40/carry_tests/counter.v
new file mode 100644
index 00000000..8906ff45
--- /dev/null
+++ b/ice40/carry_tests/counter.v
@@ -0,0 +1,9 @@
+module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
+
+ reg [3:0] ctr = 0;
+
+ always @(posedge clk)
+ ctr <= ctr + 1'b1;
+
+ assign {outa, outb, outc, outd} = ctr;
+endmodule
diff --git a/ice40/carry_tests/test.pcf b/ice40/carry_tests/test.pcf
new file mode 100644
index 00000000..8cd488bf
--- /dev/null
+++ b/ice40/carry_tests/test.pcf
@@ -0,0 +1,10 @@
+set_io clk 1
+set_io cen 2
+set_io rst 3
+set_io ina 4
+set_io inb 7
+set_io outa 8
+set_io outb 9
+set_io outc 10
+set_io outd 11
+
diff --git a/ice40/carry_tests/test.sh b/ice40/carry_tests/test.sh
new file mode 100755
index 00000000..8e028f16
--- /dev/null
+++ b/ice40/carry_tests/test.sh
@@ -0,0 +1,16 @@
+#!/usr/bin/env bash
+set -ex
+NAME=${1%.v}
+yosys -p "synth_ice40 -top top; write_json ${NAME}.json" $1
+../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc
+icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
+
+yosys -p "read_verilog +/ice40/cells_sim.v;\
+ rename chip gate;\
+ read_verilog $1;\
+ rename top gold;\
+ hierarchy;\
+ proc;\
+ clk2fflogic;\
+ miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
+ sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v