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authorClifford Wolf <clifford@clifford.at>2018-06-17 16:14:27 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-17 16:14:27 +0200
commit105cde328bb228cbba37cbd730dc60a206d5a219 (patch)
treee080ff8ed359d16b2f14dfca80a169e21fc772f2 /ice40/chip.cc
parent19b665177ed10c5e16dea587697d4e8eeadaa09b (diff)
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Updates from clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/chip.cc')
-rw-r--r--ice40/chip.cc18
1 files changed, 12 insertions, 6 deletions
diff --git a/ice40/chip.cc b/ice40/chip.cc
index 477df3d7..d92d61dd 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -82,19 +82,24 @@ Chip::Chip(ChipArgs args) : args(args)
{
#ifdef ICE40_HX1K_ONLY
if (args.type == ChipArgs::HX1K) {
- chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
+ chip_info =
+ reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
if (args.type == ChipArgs::LP384) {
- chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_384)->get();
+ chip_info =
+ reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_384)->get();
} else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
- chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_1k)->get();
+ chip_info =
+ reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
} else if (args.type == ChipArgs::UP5K) {
- chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_5k)->get();
+ chip_info =
+ reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_5k)->get();
} else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
- chip_info = reinterpret_cast<RelPtr<ChipInfoPOD>*>(chipdb_blob_8k)->get();
+ chip_info =
+ reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_8k)->get();
} else {
log_error("Unsupported iCE40 chip type.\n");
}
@@ -190,7 +195,8 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId());
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
- const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+ const BelWirePOD *bel_wires =
+ chip_info->bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) {