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authorDavid Shah <davey1576@gmail.com>2018-06-22 17:44:26 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-22 17:44:26 +0200
commit7c169c48d015d78482a6a0496c7f5bb8c3d63536 (patch)
treec906a5a692dbe6b3c4746ed34896b136f8683c6a /ice40/chipdb.py
parente5bd4764b27c86fa804700b18bcac5cf18815314 (diff)
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ice40: Preparations for extra cells support
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/chipdb.py')
-rw-r--r--ice40/chipdb.py12
1 files changed, 12 insertions, 0 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 100aaa6f..92d52288 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -59,6 +59,17 @@ beltypes["ICESTORM_LC"] = 1
beltypes["ICESTORM_RAM"] = 2
beltypes["SB_IO"] = 3
beltypes["SB_GB"] = 4
+beltypes["PLL"] = 5
+beltypes["WARMBOOT"] = 6
+beltypes["MAC16"] = 7
+beltypes["HFOSC"] = 8
+beltypes["LFOSC"] = 9
+beltypes["I2C"] = 10
+beltypes["SPI"] = 11
+beltypes["IO_I3C"] = 12
+beltypes["LEDDA_IP"] = 13
+beltypes["RGBA_DRV"] = 14
+beltypes["SPRAM"] = 15
tiletypes["NONE"] = 0
tiletypes["LOGIC"] = 1
@@ -189,6 +200,7 @@ def pipdelay(src, dst):
assert 0
+
def init_tiletypes(device):
global num_tile_types, tile_sizes, tile_bits
if device == "5k":