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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-19 18:43:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-08-19 18:43:38 +0200 |
| commit | 801f63098348878d1dcd5e88735afeae014d7f22 (patch) | |
| tree | 7e218831b7965003b96200bdda510a71a5275fde /ice40/chipdb.py | |
| parent | 49d3857f9728b89ab8bac000f5dc0ed8627d23c9 (diff) | |
| download | nextpnr-801f63098348878d1dcd5e88735afeae014d7f22.tar.gz nextpnr-801f63098348878d1dcd5e88735afeae014d7f22.tar.bz2 nextpnr-801f63098348878d1dcd5e88735afeae014d7f22.zip | |
Add more missing iCE40 gfx (LP/HX is complete now)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index c33d736c..5b2f3e57 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -727,10 +727,6 @@ def add_pip(src, dst, flags=0): pip_xy[(src, dst)] = (x, y, 0, len(switches) - 1, flags) -# Add virtual padin wires -for i in range(8): - add_wire(0, 0, "padin_%d" % i) - def add_bel_input(bel, wire, port): if wire not in wire_belports: wire_belports[wire] = set() |