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authorClifford Wolf <clifford@clifford.at>2018-06-20 19:22:03 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-20 19:22:03 +0200
commit9475997a2df199d6dc27375978b56a08908d096e (patch)
tree26dd8479b4985fa765f377bc23edb57c4b82dc15 /ice40/chipdb.py
parent2da90889efb194be4140ebfd5893bdf0ced223f3 (diff)
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Improve --tmfuzz mode and iCE40 delay estimator
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/chipdb.py')
-rw-r--r--ice40/chipdb.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 82b8be8b..fe25c1f1 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -72,10 +72,10 @@ tiletypes["RAMT"] = 4
wiretypes["LOCAL"] = 1
wiretypes["GLOBAL"] = 2
-wiretypes["SP4_VERT"] = 5
-wiretypes["SP4_HORZ"] = 6
-wiretypes["SP12_HORZ"] = 7
-wiretypes["SP12_VERT"] = 8
+wiretypes["SP4_VERT"] = 3
+wiretypes["SP4_HORZ"] = 4
+wiretypes["SP12_HORZ"] = 5
+wiretypes["SP12_VERT"] = 6
def maj_wire_name(name):
if name[2].startswith("lutff_"):