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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-04 10:32:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-08-04 10:32:07 +0200 |
| commit | 96291f17aac62f9b58370c67e4eeff71adc848c1 (patch) | |
| tree | a957f13f0dacfa4ac0066f2f872ed4d06dba7e61 /ice40/chipdb.py | |
| parent | 8d372b86f3aed86c7a8ef7869e92335bd965c2ae (diff) | |
| parent | f5a1b93f0e9348437ece7fb7d46ac69af98536d0 (diff) | |
| download | nextpnr-96291f17aac62f9b58370c67e4eeff71adc848c1.tar.gz nextpnr-96291f17aac62f9b58370c67e4eeff71adc848c1.tar.bz2 nextpnr-96291f17aac62f9b58370c67e4eeff71adc848c1.zip | |
Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 0227ab6a..c1819481 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -787,7 +787,9 @@ tmport_to_portpin = { "WCLKE": "WCLKE", "WE": "WE", "posedge:CLOCK": "CLOCK", - "posedge:SLEEP": "SLEEP" + "posedge:SLEEP": "SLEEP", + "USERSIGNALTOGLOBALBUFFER": "USER_SIGNAL_TO_GLOBAL_BUFFER", + "GLOBALBUFFEROUTPUT": "GLOBAL_BUFFER_OUTPUT" } for i in range(16): @@ -815,6 +817,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db): cell_timings[bel_type] = timing_entries add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings) +add_cell_timingdata("SB_GB", "ICE_GB", fast_timings, slow_timings) + if dev_name != "384": add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) if dev_name == "5k": |