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| author | David Shah <davey1576@gmail.com> | 2019-02-21 20:34:23 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2019-02-21 20:34:23 +0000 |
| commit | a05f6b261ecf437f8618da6f7dc95d860b429edd (patch) | |
| tree | 341cf008aedfc83d540768170ab1b4c1246b7bd7 /ice40/chipdb.py | |
| parent | e8d3aaaf34895a073e4023192d97fc936d090990 (diff) | |
| download | nextpnr-a05f6b261ecf437f8618da6f7dc95d860b429edd.tar.gz nextpnr-a05f6b261ecf437f8618da6f7dc95d860b429edd.tar.bz2 nextpnr-a05f6b261ecf437f8618da6f7dc95d860b429edd.zip | |
ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 96231b26..f296cb2b 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -954,6 +954,25 @@ def add_bel_ec(ec): add_pll_clock_output(bel, ec, entry) else: extra_cell_config[bel].append(entry) + if ectype == "MAC16": + if y == 5: + last_dsp_y = 0 # dummy, but the wire is needed + elif y == 10: + last_dsp_y = 5 + elif y == 15: + last_dsp_y = 10 + elif y == 23: + last_dsp_y = 23 + else: + assert False, "unknown DSP y " + str(y) + wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout") + wire_signextout = add_wire(x, y, "dsp/signextout") + wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco") + wire_accumco = add_wire(x, y, "dsp/accumco") + add_bel_input(bel, wire_signextin, "SIGNEXTIN") + add_bel_output(bel, wire_signextout, "SIGNEXTOUT") + add_bel_input(bel, wire_accumci, "ACCUMCI") + add_bel_output(bel, wire_accumco, "ACCUMCO") cell_timings = {} tmport_to_constids = { |