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| author | David Shah <davey1576@gmail.com> | 2018-08-02 16:02:43 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-08-02 16:02:51 +0200 |
| commit | a7269a685ec57f855f0c46b0adbd6aa8e9a03843 (patch) | |
| tree | 04b48053e771c51d002390c79990b88af2367743 /ice40/chipdb.py | |
| parent | c0aaac8dfab08f753bdb1f4d4e0315b65bbaf98a (diff) | |
| download | nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.tar.gz nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.tar.bz2 nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.zip | |
ice40: Use real cell timings
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 842ae2a2..3f9f4e65 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -666,14 +666,14 @@ def add_bel_ec(ec): cell_timings = {} tmport_to_portpin = { "posedge:clk": "CLK", - "ce": "CE", + "ce": "CEN", "sr": "SR", "in0": "I0", "in1": "I1", "in2": "I2", "in3": "I3", "carryin": "CIN", - "carrout": "COUT", + "carryout": "COUT", "lcout": "O", "ltout": "LO", "posedge:RCLK": "RCLK", @@ -711,8 +711,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db): cell_timings[bel_type] = timing_entries add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings) -add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) - +if dev_name != "384": + add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) if dev_name == "5k": add_cell_timingdata("SPRAM", "SB_SPRAM256KA", fast_timings, slow_timings) @@ -1154,6 +1154,7 @@ bba.u32(len(pipinfo), "num_pips") bba.u32(len(switchinfo), "num_switches") bba.u32(len(extra_cell_config), "num_belcfgs") bba.u32(len(packageinfo), "num_packages") +bba.u32(len(cell_timings), "num_timing_cells") bba.r("bel_data_%s" % dev_name, "bel_data") bba.r("wire_data_%s" % dev_name, "wire_data") bba.r("pip_data_%s" % dev_name, "pip_data") @@ -1161,6 +1162,6 @@ bba.r("tile_grid_%s" % dev_name, "tile_grid") bba.r("bits_info_%s" % dev_name, "bits_info") bba.r("bel_config_%s" % dev_name if len(extra_cell_config) > 0 else None, "bel_config") bba.r("package_info_%s" % dev_name, "packages_data") -bba.r("cell_timing_%s" % dev_name, "cell_timing") +bba.r("cell_timings_%s" % dev_name, "cell_timing") bba.pop() |