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| author | gatecat <gatecat@ds0.me> | 2022-09-14 09:24:49 +0200 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-09-14 09:24:49 +0200 |
| commit | 0a8c411692629b4748673b11f8dca8c3db7552fb (patch) | |
| tree | f686df684cab4f79f106f6ee569a0f0208f7bfba /ice40 | |
| parent | f1349e114f3a16ccd002e8513339e18f5be4d31b (diff) | |
| download | nextpnr-0a8c411692629b4748673b11f8dca8c3db7552fb.tar.gz nextpnr-0a8c411692629b4748673b11f8dca8c3db7552fb.tar.bz2 nextpnr-0a8c411692629b4748673b11f8dca8c3db7552fb.zip | |
ice40: Fix UltraPlus BRAM clock polarity
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/bitstream.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 3e50c065..2e1a6d4e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out) bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W); int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE); int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE); - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); - + if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); + } else { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + } set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); |