Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

8 files changed, 165 insertions, 338 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index d374b764..1a9c11df 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -25,16 +25,13 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 PlaceValidityChecker::PlaceValidityChecker(Context *ctx)
-        : ctx(ctx), id_icestorm_lc(ctx, "ICESTORM_LC"), id_sb_io(ctx, "SB_IO"),
-          id_sb_gb(ctx, "SB_GB"), id_cen(ctx, "CEN"), id_clk(ctx, "CLK"),
-          id_sr(ctx, "SR"), id_i0(ctx, "I0"), id_i1(ctx, "I1"),
-          id_i2(ctx, "I2"), id_i3(ctx, "I3"), id_dff_en(ctx, "DFF_ENABLE"),
-          id_neg_clk(ctx, "NEG_CLK")
+        : ctx(ctx), id_icestorm_lc(ctx, "ICESTORM_LC"), id_sb_io(ctx, "SB_IO"), id_sb_gb(ctx, "SB_GB"),
+          id_cen(ctx, "CEN"), id_clk(ctx, "CLK"), id_sr(ctx, "SR"), id_i0(ctx, "I0"), id_i1(ctx, "I1"),
+          id_i2(ctx, "I2"), id_i3(ctx, "I3"), id_dff_en(ctx, "DFF_ENABLE"), id_neg_clk(ctx, "NEG_CLK")
 {
 }
 
-static const NetInfo *get_net_or_empty(const CellInfo *cell,
-                                       const IdString port)
+static const NetInfo *get_net_or_empty(const CellInfo *cell, const IdString port)
 {
     auto found = cell->ports.find(port);
     if (found != cell->ports.end())
@@ -43,8 +40,7 @@ static const NetInfo *get_net_or_empty(const CellInfo *cell,
         return nullptr;
 };
 
-bool PlaceValidityChecker::logicCellsCompatible(
-        const Context *ctx, const std::vector<const CellInfo *> &cells)
+bool PlaceValidityChecker::logicCellsCompatible(const Context *ctx, const std::vector<const CellInfo *> &cells)
 {
     bool dffs_exist = false, dffs_neg = false;
     const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
@@ -80,10 +76,8 @@ bool PlaceValidityChecker::logicCellsCompatible(
             }
         }
 
-        const NetInfo *i0 = get_net_or_empty(cell, id_i0),
-                      *i1 = get_net_or_empty(cell, id_i1),
-                      *i2 = get_net_or_empty(cell, id_i2),
-                      *i3 = get_net_or_empty(cell, id_i3);
+        const NetInfo *i0 = get_net_or_empty(cell, id_i0), *i1 = get_net_or_empty(cell, id_i1),
+                      *i2 = get_net_or_empty(cell, id_i2), *i3 = get_net_or_empty(cell, id_i3);
         if (i0 != nullptr)
             locals_count++;
         if (i1 != nullptr)
@@ -140,15 +134,13 @@ bool PlaceValidityChecker::isValidBelForCell(CellInfo *cell, BelId bel)
     } else if (cell->type == id_sb_gb) {
         bool is_reset = false, is_cen = false;
         assert(cell->ports.at(ctx->id("GLOBAL_BUFFER_OUTPUT")).net != nullptr);
-        for (auto user :
-             cell->ports.at(ctx->id("GLOBAL_BUFFER_OUTPUT")).net->users) {
+        for (auto user : cell->ports.at(ctx->id("GLOBAL_BUFFER_OUTPUT")).net->users) {
             if (is_reset_port(ctx, user))
                 is_reset = true;
             if (is_enable_port(ctx, user))
                 is_cen = true;
         }
-        IdString glb_net = ctx->getWireName(
-                ctx->getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
+        IdString glb_net = ctx->getWireName(ctx->getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
         int glb_id = std::stoi(std::string("") + glb_net.str(ctx).back());
         if (is_reset && is_cen)
             return false;
diff --git a/ice40/arch_place.h b/ice40/arch_place.h
index e90f2874..84ad2d21 100644
--- a/ice40/arch_place.h
+++ b/ice40/arch_place.h
@@ -39,8 +39,7 @@ class PlaceValidityChecker
     bool isBelLocationValid(BelId bel);
 
   private:
-    bool logicCellsCompatible(const Context *ctx,
-                              const std::vector<const CellInfo *> &cells);
+    bool logicCellsCompatible(const Context *ctx, const std::vector<const CellInfo *> &cells);
     Context *ctx;
     IdString id_icestorm_lc, id_sb_io, id_sb_gb;
     IdString id_cen, id_clk, id_sr;
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 58c2e754..0e387c72 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -28,8 +28,7 @@ inline TileType tile_at(const Context *ctx, int x, int y)
     return ctx->chip_info->tile_grid[y * ctx->chip_info->width + x];
 }
 
-const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
-                                  const std::string &name)
+const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &name)
 {
     for (int i = 0; i < tile.num_config_entries; i++) {
         if (std::string(tile.entries[i].name.get()) == name) {
@@ -39,8 +38,7 @@ const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
     assert(false);
 }
 
-std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi,
-                                             int8_t x, int8_t y, int8_t z)
+std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi, int8_t x, int8_t y, int8_t z)
 {
     for (int i = 0; i < bi.num_ierens; i++) {
         auto ie = bi.ierens[i];
@@ -52,9 +50,8 @@ std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi,
     return std::make_tuple(-1, -1, -1);
 };
 
-void set_config(const TileInfoPOD &ti,
-                std::vector<std::vector<int8_t>> &tile_cfg,
-                const std::string &name, bool value, int index = -1)
+void set_config(const TileInfoPOD &ti, std::vector<std::vector<int8_t>> &tile_cfg, const std::string &name, bool value,
+                int index = -1)
 {
     const ConfigEntryPOD &cfg = find_config(ti, name);
     if (index == -1) {
@@ -68,8 +65,7 @@ void set_config(const TileInfoPOD &ti,
         int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col);
         cbit = value;
         if (cbit && !value)
-            log_error("clearing already set config bit %s[%d]", name.c_str(),
-                      index);
+            log_error("clearing already set config bit %s[%d]", name.c_str(), index);
     }
 }
 
@@ -82,8 +78,7 @@ int get_param_or_def(const CellInfo *cell, const IdString param, int defval = 0)
         return defval;
 }
 
-std::string get_param_str_or_def(const CellInfo *cell, const IdString param,
-                                 std::string defval = "")
+std::string get_param_str_or_def(const CellInfo *cell, const IdString param, std::string defval = "")
 {
     auto found = cell->params.find(param);
     if (found != cell->params.end())
@@ -136,12 +131,8 @@ void write_asc(const Context *ctx, std::ostream &out)
             const PipInfoPOD &pi = ci.pip_data[pip.index];
             const SwitchInfoPOD &swi = bi.switches[pi.switch_index];
             for (int i = 0; i < swi.num_bits; i++) {
-                bool val =
-                        (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0;
-                int8_t &cbit = config.at(swi.y)
-                                       .at(swi.x)
-                                       .at(swi.cbits[i].row)
-                                       .at(swi.cbits[i].col);
+                bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0;
+                int8_t &cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col);
                 if (bool(cbit) != 0)
                     assert(false);
                 cbit = val;
@@ -152,24 +143,19 @@ void write_asc(const Context *ctx, std::ostream &out)
     for (auto cell : ctx->cells) {
         BelId bel = cell.second->bel;
         if (bel == BelId()) {
-            std::cout << "Found unplaced cell " << cell.first.str(ctx)
-                      << " while generating bitstream!" << std::endl;
+            std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl;
             continue;
         }
         const BelInfoPOD &beli = ci.bel_data[bel.index];
         int x = beli.x, y = beli.y, z = beli.z;
         if (cell.second->type == ctx->id("ICESTORM_LC")) {
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
-            unsigned lut_init =
-                    get_param_or_def(cell.second, ctx->id("LUT_INIT"));
+            unsigned lut_init = get_param_or_def(cell.second, ctx->id("LUT_INIT"));
             bool neg_clk = get_param_or_def(cell.second, ctx->id("NEG_CLK"));
-            bool dff_enable =
-                    get_param_or_def(cell.second, ctx->id("DFF_ENABLE"));
+            bool dff_enable = get_param_or_def(cell.second, ctx->id("DFF_ENABLE"));
             bool async_sr = get_param_or_def(cell.second, ctx->id("ASYNC_SR"));
-            bool set_noreset =
-                    get_param_or_def(cell.second, ctx->id("SET_NORESET"));
-            bool carry_enable =
-                    get_param_or_def(cell.second, ctx->id("CARRY_ENABLE"));
+            bool set_noreset = get_param_or_def(cell.second, ctx->id("SET_NORESET"));
+            bool carry_enable = get_param_or_def(cell.second, ctx->id("CARRY_ENABLE"));
             std::vector<bool> lc(20, false);
             // From arachne-pnr
             static std::vector<int> lut_perm = {
@@ -185,23 +171,17 @@ void write_asc(const Context *ctx, std::ostream &out)
             lc.at(19) = async_sr;
 
             for (int i = 0; i < 20; i++)
-                set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z),
-                           lc.at(i), i);
+                set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z), lc.at(i), i);
             if (dff_enable)
                 set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
         } else if (cell.second->type == ctx->id("SB_IO")) {
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-            unsigned pin_type =
-                    get_param_or_def(cell.second, ctx->id("PIN_TYPE"));
-            bool neg_trigger =
-                    get_param_or_def(cell.second, ctx->id("NEG_TRIGGER"));
+            unsigned pin_type = get_param_or_def(cell.second, ctx->id("PIN_TYPE"));
+            bool neg_trigger = get_param_or_def(cell.second, ctx->id("NEG_TRIGGER"));
             bool pullup = get_param_or_def(cell.second, ctx->id("PULLUP"));
             for (int i = 0; i < 6; i++) {
                 bool val = (pin_type >> i) & 0x01;
-                set_config(ti, config.at(y).at(x),
-                           "IOB_" + std::to_string(z) + ".PINTYPE_" +
-                                   std::to_string(i),
-                           val);
+                set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
             }
 
             auto ieren = get_ieren(bi, x, y, z);
@@ -210,33 +190,24 @@ void write_asc(const Context *ctx, std::ostream &out)
             assert(iez != -1);
 
             bool input_en = false;
-            if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] !=
-                 IdString()) ||
-                (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] !=
-                 IdString())) {
+            if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||
+                (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {
                 input_en = true;
             }
 
-            if (ctx->args.type == ArchArgs::LP1K ||
-                ctx->args.type == ArchArgs::HX1K) {
-                set_config(ti, config.at(iey).at(iex),
-                           "IoCtrl.IE_" + std::to_string(iez), !input_en);
-                set_config(ti, config.at(iey).at(iex),
-                           "IoCtrl.REN_" + std::to_string(iez), !pullup);
+            if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
+                set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), !input_en);
+                set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
             } else {
-                set_config(ti, config.at(iey).at(iex),
-                           "IoCtrl.IE_" + std::to_string(iez), input_en);
-                set_config(ti, config.at(iey).at(iex),
-                           "IoCtrl.REN_" + std::to_string(iez), !pullup);
+                set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), input_en);
+                set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
             }
 
             if (ctx->args.type == ArchArgs::UP5K) {
                 if (iez == 0) {
-                    set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39",
-                               !pullup);
+                    set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup);
                 } else if (iez == 1) {
-                    set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35",
-                               !pullup);
+                    set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", !pullup);
                 }
             }
         } else if (cell.second->type == ctx->id("SB_GB")) {
@@ -246,29 +217,21 @@ void write_asc(const Context *ctx, std::ostream &out)
             int x = beli.x, y = beli.y;
             const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
             const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB];
-            if (!(ctx->args.type == ArchArgs::LP1K ||
-                  ctx->args.type == ArchArgs::HX1K)) {
-                set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp",
-                           true);
+            if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
+                set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true);
             }
             bool negclk_r = get_param_or_def(cell.second, ctx->id("NEG_CLK_R"));
             bool negclk_w = get_param_or_def(cell.second, ctx->id("NEG_CLK_W"));
-            int write_mode =
-                    get_param_or_def(cell.second, ctx->id("WRITE_MODE"));
+            int write_mode = get_param_or_def(cell.second, ctx->id("WRITE_MODE"));
             int read_mode = get_param_or_def(cell.second, ctx->id("READ_MODE"));
             set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
             set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
 
-            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0",
-                       write_mode & 0x1);
-            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1",
-                       write_mode & 0x2);
-            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2",
-                       read_mode & 0x1);
-            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3",
-                       read_mode & 0x2);
-        } else if (cell.second->type == ctx->id("SB_WARMBOOT") ||
-                   cell.second->type == ctx->id("ICESTORM_LFOSC")) {
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", read_mode & 0x2);
+        } else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC")) {
             // No config needed
         } else {
             assert(false);
@@ -276,8 +239,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     }
     // Set config bits in unused IO and RAM
     for (auto bel : ctx->getBels()) {
-        if (ctx->bel_to_cell[bel.index] == IdString() &&
-            ctx->getBelType(bel) == TYPE_SB_IO) {
+        if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) {
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
@@ -285,21 +247,16 @@ void write_asc(const Context *ctx, std::ostream &out)
             int iex, iey, iez;
             std::tie(iex, iey, iez) = ieren;
             if (iez != -1) {
-                if (ctx->args.type == ArchArgs::LP1K ||
-                    ctx->args.type == ArchArgs::HX1K) {
-                    set_config(ti, config.at(iey).at(iex),
-                               "IoCtrl.IE_" + std::to_string(iez), true);
-                    set_config(ti, config.at(iey).at(iex),
-                               "IoCtrl.REN_" + std::to_string(iez), false);
+                if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
+                    set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true);
+                    set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false);
                 }
             }
-        } else if (ctx->bel_to_cell[bel.index] == IdString() &&
-                   ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {
+        } else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
-            if ((ctx->args.type == ArchArgs::LP1K ||
-                 ctx->args.type == ArchArgs::HX1K)) {
+            if ((ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
                 set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
             }
         }
@@ -313,67 +270,48 @@ void write_asc(const Context *ctx, std::ostream &out)
 
             // set all ColBufCtrl bits (FIXME)
             bool setColBufCtrl = true;
-            if (ctx->args.type == ArchArgs::LP1K ||
-                ctx->args.type == ArchArgs::HX1K) {
+            if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
                 if (tile == TILE_RAMB || tile == TILE_RAMT) {
                     setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13);
                 } else {
                     setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13);
                 }
-            } else if (ctx->args.type == ArchArgs::LP8K ||
-                       ctx->args.type == ArchArgs::HX8K) {
+            } else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K) {
                 setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
             } else if (ctx->args.type == ArchArgs::UP5K) {
-                setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 ||
-                                 y == 26 || y == 27);
+                setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27);
             }
             if (setColBufCtrl) {
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6",
-                           true);
-                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7",
-                           true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6", true);
+                set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7", true);
             }
 
             // Weird UltraPlus bits
-            if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 ||
-                tile == TILE_DSP3 || tile == TILE_IPCON) {
+            if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 ||
+                tile == TILE_IPCON) {
                 if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) {
                     // Mystery bits not set in this one tile
                 } else {
                     for (int lc_idx = 0; lc_idx < 8; lc_idx++) {
                         static const std::vector<int> ip_dsp_lut_perm = {
-                                4, 14, 15, 5, 6, 16, 17, 7,
-                                3, 13, 12, 2, 1, 11, 10, 0,
+                                4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
                         };
                         for (int i = 0; i < 16; i++)
-                            set_config(ti, config.at(y).at(x),
-                                       "LC_" + std::to_string(lc_idx),
-                                       ((i % 8) >= 4), ip_dsp_lut_perm.at(i));
+                            set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4),
+                                       ip_dsp_lut_perm.at(i));
                         if (tile == TILE_IPCON)
                             set_config(ti, config.at(y).at(x),
-                                       "Cascade.IPCON_LC0" +
-                                               std::to_string(lc_idx) +
-                                               "_inmux02_5",
-                                       true);
+                                       "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
                         else
                             set_config(ti, config.at(y).at(x),
-                                       "Cascade.MULT" +
-                                               std::to_string(
-                                                       int(tile - TILE_DSP0)) +
-                                               "_LC0" + std::to_string(lc_idx) +
-                                               "_inmux02_5",
+                                       "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
+                                               std::to_string(lc_idx) + "_inmux02_5",
                                        true);
                     }
                 }
@@ -441,17 +379,15 @@ void write_asc(const Context *ctx, std::ostream &out)
                 out << ".ram_data " << x << " " << y << std::endl;
                 for (int w = 0; w < 16; w++) {
                     std::vector<bool> bits(256);
-                    std::string init = get_param_str_or_def(
-                            cell.second,
-                            ctx->id(std::string("INIT_") + get_hexdigit(w)));
+                    std::string init =
+                            get_param_str_or_def(cell.second, ctx->id(std::string("INIT_") + get_hexdigit(w)));
                     assert(init != "");
                     for (size_t i = 0; i < init.size(); i++) {
                         bool val = (init.at((init.size() - 1) - i) == '1');
                         bits.at(i) = val;
                     }
                     for (int i = bits.size() - 4; i >= 0; i -= 4) {
-                        int c = bits.at(i) + (bits.at(i + 1) << 1) +
-                                (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
+                        int c = bits.at(i) + (bits.at(i + 1) << 1) + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
                         out << char(std::tolower(get_hexdigit(c)));
                     }
                     out << std::endl;
diff --git a/ice40/cells.cc b/ice40/cells.cc
index f34b7511..faaabba0 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -24,8 +24,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, std::string name,
-              PortType dir)
+void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
 {
     IdString id = ctx->id(name);
     cell->ports[id] = PortInfo{id, nullptr, dir};
@@ -36,8 +35,7 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name)
     static int auto_idx = 0;
     CellInfo *new_cell = new CellInfo();
     if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" +
-                                 std::to_string(auto_idx++));
+        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
     } else {
         new_cell->name = ctx->id(name);
     }
@@ -143,8 +141,7 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
     }
 }
 
-void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
-               bool pass_thru_lut)
+void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 {
     lc->params[ctx->id("DFF_ENABLE")] = "1";
     std::string config = dff->type.str(ctx).substr(6);
@@ -214,22 +211,18 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
         assert(false);
     }
     NetInfo *donet = sbio->ports.at(ctx->id("D_OUT_0")).net;
-    CellInfo *tbuf =
-            net_driven_by(ctx, donet,
-                          [](const Context *ctx, const CellInfo *cell) {
-                              return cell->type == ctx->id("$_TBUF_");
-                          },
-                          ctx->id("Y"));
+    CellInfo *tbuf = net_driven_by(
+            ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
+            ctx->id("Y"));
     if (tbuf) {
         sbio->params[ctx->id("PIN_TYPE")] = "41";
         replace_port(tbuf, ctx->id("A"), sbio, ctx->id("D_OUT_0"));
         replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE"));
         ctx->nets.erase(donet->name);
         if (!donet->users.empty())
-            log_error(
-                    "unsupported tristate IO pattern for IO buffer '%s', "
-                    "instantiate SB_IO manually to ensure correct behaviour\n",
-                    nxio->name.c_str(ctx));
+            log_error("unsupported tristate IO pattern for IO buffer '%s', "
+                      "instantiate SB_IO manually to ensure correct behaviour\n",
+                      nxio->name.c_str(ctx));
         ctx->cells.erase(tbuf->name);
     }
 }
diff --git a/ice40/cells.h b/ice40/cells.h
index 29331445..7b5e63d9 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -30,89 +30,53 @@ NEXTPNR_NAMESPACE_BEGIN
 CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_LUT4");
-}
+inline bool is_lut(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LUT4"); }
 
 // Return true if a cell is a flipflop
 inline bool is_ff(const Context *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_DFF") ||
-           cell->type == ctx->id("SB_DFFE") ||
-           cell->type == ctx->id("SB_DFFSR") ||
-           cell->type == ctx->id("SB_DFFR") ||
-           cell->type == ctx->id("SB_DFFSS") ||
-           cell->type == ctx->id("SB_DFFS") ||
-           cell->type == ctx->id("SB_DFFESR") ||
-           cell->type == ctx->id("SB_DFFER") ||
-           cell->type == ctx->id("SB_DFFESS") ||
-           cell->type == ctx->id("SB_DFFES") ||
-           cell->type == ctx->id("SB_DFFN") ||
-           cell->type == ctx->id("SB_DFFNE") ||
-           cell->type == ctx->id("SB_DFFNSR") ||
-           cell->type == ctx->id("SB_DFFNR") ||
-           cell->type == ctx->id("SB_DFFNSS") ||
-           cell->type == ctx->id("SB_DFFNS") ||
-           cell->type == ctx->id("SB_DFFNESR") ||
-           cell->type == ctx->id("SB_DFFNER") ||
-           cell->type == ctx->id("SB_DFFNESS") ||
-           cell->type == ctx->id("SB_DFFNES");
+    return cell->type == ctx->id("SB_DFF") || cell->type == ctx->id("SB_DFFE") || cell->type == ctx->id("SB_DFFSR") ||
+           cell->type == ctx->id("SB_DFFR") || cell->type == ctx->id("SB_DFFSS") || cell->type == ctx->id("SB_DFFS") ||
+           cell->type == ctx->id("SB_DFFESR") || cell->type == ctx->id("SB_DFFER") ||
+           cell->type == ctx->id("SB_DFFESS") || cell->type == ctx->id("SB_DFFES") ||
+           cell->type == ctx->id("SB_DFFN") || cell->type == ctx->id("SB_DFFNE") ||
+           cell->type == ctx->id("SB_DFFNSR") || cell->type == ctx->id("SB_DFFNR") ||
+           cell->type == ctx->id("SB_DFFNSS") || cell->type == ctx->id("SB_DFFNS") ||
+           cell->type == ctx->id("SB_DFFNESR") || cell->type == ctx->id("SB_DFFNER") ||
+           cell->type == ctx->id("SB_DFFNESS") || cell->type == ctx->id("SB_DFFNES");
 }
 
-inline bool is_carry(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_CARRY");
-}
+inline bool is_carry(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_CARRY"); }
 
-inline bool is_lc(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("ICESTORM_LC");
-}
+inline bool is_lc(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("ICESTORM_LC"); }
 
 // Return true if a cell is a SB_IO
-inline bool is_sb_io(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_IO");
-}
+inline bool is_sb_io(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_IO"); }
 
 // Return true if a cell is a global buffer
-inline bool is_gbuf(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_GB");
-}
+inline bool is_gbuf(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_GB"); }
 
 // Return true if a cell is a RAM
 inline bool is_ram(const Context *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_RAM40_4K") ||
-           cell->type == ctx->id("SB_RAM40_4KNR") ||
-           cell->type == ctx->id("SB_RAM40_4KNW") ||
-           cell->type == ctx->id("SB_RAM40_4KNRNW");
+    return cell->type == ctx->id("SB_RAM40_4K") || cell->type == ctx->id("SB_RAM40_4KNR") ||
+           cell->type == ctx->id("SB_RAM40_4KNW") || cell->type == ctx->id("SB_RAM40_4KNRNW");
 }
 
-inline bool is_sb_lfosc(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_LFOSC");
-}
+inline bool is_sb_lfosc(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LFOSC"); }
 
-inline bool is_sb_hfosc(const Context *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_HFOSC");
-}
+inline bool is_sb_hfosc(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_HFOSC"); }
 
 // Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
 // can be reconnected
-void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc,
-               bool no_dff = true);
+void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
 
 // Convert a SB_DFFx primitive to (part of) an ICESTORM_LC, setting parameters
 // and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
 // be configured as pass through and D connected to I0, otherwise D will be
 // ignored
-void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
-               bool pass_thru_lut = false);
+void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
 
 // Convert a nextpnr IO buffer to a SB_IO
 void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio);
diff --git a/ice40/pack.cc b/ice40/pack.cc
index e6be502f..85c1af8c 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -38,18 +38,14 @@ static void pack_lut_lutffs(Context *ctx)
     for (auto cell : sorted(ctx->cells)) {
         CellInfo *ci = cell.second;
         if (ctx->verbose)
-            log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx),
-                     ci->type.c_str(ctx));
+            log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
         if (is_lut(ctx, ci)) {
-            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"),
-                                               ci->name.str(ctx) + "_LC");
-            std::copy(ci->attrs.begin(), ci->attrs.end(),
-                      std::inserter(packed->attrs, packed->attrs.begin()));
+            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_LC");
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
             if (ctx->verbose)
-                log_info("packed cell %s into %s\n", ci->name.c_str(ctx),
-                         packed->name.c_str(ctx));
+                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
             // See if we can pack into a DFF
             // TODO: LUT cascade
             NetInfo *o = ci->ports.at(ctx->id("O")).net;
@@ -60,8 +56,7 @@ static void pack_lut_lutffs(Context *ctx)
                 if (ctx->verbose)
                     log_info("found attached dff %s\n", dff->name.c_str(ctx));
                 auto dff_bel = dff->attrs.find(ctx->id("BEL"));
-                if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() &&
-                    lut_bel->second != dff_bel->second) {
+                if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
                     // Locations don't match, can't pack
                 } else {
                     lut_to_lc(ctx, ci, packed, false);
@@ -71,8 +66,7 @@ static void pack_lut_lutffs(Context *ctx)
                         packed->attrs[ctx->id("BEL")] = dff_bel->second;
                     packed_cells.insert(dff->name);
                     if (ctx->verbose)
-                        log_info("packed cell %s into %s\n",
-                                 dff->name.c_str(ctx), packed->name.c_str(ctx));
+                        log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
                     packed_dff = true;
                 }
             }
@@ -100,13 +94,10 @@ static void pack_nonlut_ffs(Context *ctx)
     for (auto cell : sorted(ctx->cells)) {
         CellInfo *ci = cell.second;
         if (is_ff(ctx, ci)) {
-            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"),
-                                               ci->name.str(ctx) + "_DFFLC");
-            std::copy(ci->attrs.begin(), ci->attrs.end(),
-                      std::inserter(packed->attrs, packed->attrs.begin()));
+            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_DFFLC");
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
             if (ctx->verbose)
-                log_info("packed cell %s into %s\n", ci->name.c_str(ctx),
-                         packed->name.c_str(ctx));
+                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
             dff_to_lc(ctx, ci, packed, true);
@@ -131,15 +122,11 @@ static void pack_carries(Context *ctx)
         CellInfo *ci = cell.second;
         if (is_carry(ctx, ci)) {
             packed_cells.insert(cell.first);
-            CellInfo *carry_ci_lc =
-                    net_only_drives(ctx, ci->ports.at(ctx->id("CI")).net, is_lc,
-                                    ctx->id("I3"), false);
+            CellInfo *carry_ci_lc = net_only_drives(ctx, ci->ports.at(ctx->id("CI")).net, is_lc, ctx->id("I3"), false);
             if (!ci->ports.at(ctx->id("I0")).net)
-                log_error("SB_CARRY '%s' has disconnected port I0\n",
-                          cell.first.c_str(ctx));
+                log_error("SB_CARRY '%s' has disconnected port I0\n", cell.first.c_str(ctx));
             if (!ci->ports.at(ctx->id("I1")).net)
-                log_error("SB_CARRY '%s' has disconnected port I1\n",
-                          cell.first.c_str(ctx));
+                log_error("SB_CARRY '%s' has disconnected port I1\n", cell.first.c_str(ctx));
 
             std::unordered_set<IdString> i0_matches, i1_matches;
             auto &i0_usrs = ci->ports.at(ctx->id("I0")).net->users;
@@ -154,8 +141,7 @@ static void pack_carries(Context *ctx)
                     i1_matches.insert(usr.cell->name);
             }
             std::set<IdString> carry_lcs;
-            std::set_intersection(i0_matches.begin(), i0_matches.end(),
-                                  i1_matches.begin(), i1_matches.end(),
+            std::set_intersection(i0_matches.begin(), i0_matches.end(), i1_matches.begin(), i1_matches.end(),
                                   std::inserter(carry_lcs, carry_lcs.begin()));
             CellInfo *carry_lc = nullptr;
             if (carry_ci_lc) {
@@ -167,27 +153,22 @@ static void pack_carries(Context *ctx)
                 carry_lc = carry_ci_lc;
             } else {
                 if (carry_lcs.empty())
-                    log_error(
-                            "SB_CARRY '%s' cannot be packed into any logic "
-                            "cell (no logic cell connects to both I0 and I1)\n",
-                            cell.first.c_str(ctx));
+                    log_error("SB_CARRY '%s' cannot be packed into any logic "
+                              "cell (no logic cell connects to both I0 and I1)\n",
+                              cell.first.c_str(ctx));
                 carry_lc = ctx->cells.at(*carry_lcs.begin());
             }
             carry_lc->attrs[ctx->id("CARRY_ENABLE")] = "1";
             replace_port(ci, ctx->id("CI"), carry_lc, ctx->id("CIN"));
             replace_port(ci, ctx->id("CO"), carry_lc, ctx->id("COUT"));
 
-            i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(),
-                                         [ci, ctx](const PortRef &pr) {
-                                             return pr.cell == ci &&
-                                                    pr.port == ctx->id("I0");
-                                         }));
-
-            i1_usrs.erase(std::remove_if(i1_usrs.begin(), i1_usrs.end(),
-                                         [ci, ctx](const PortRef &pr) {
-                                             return pr.cell == ci &&
-                                                    pr.port == ctx->id("I1");
-                                         }));
+            i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(), [ci, ctx](const PortRef &pr) {
+                return pr.cell == ci && pr.port == ctx->id("I0");
+            }));
+
+            i1_usrs.erase(std::remove_if(i1_usrs.begin(), i1_usrs.end(), [ci, ctx](const PortRef &pr) {
+                return pr.cell == ci && pr.port == ctx->id("I1");
+            }));
         }
     }
     for (auto pcell : packed_cells) {
@@ -206,30 +187,24 @@ static void pack_ram(Context *ctx)
     for (auto cell : sorted(ctx->cells)) {
         CellInfo *ci = cell.second;
         if (is_ram(ctx, ci)) {
-            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_RAM"),
-                                               ci->name.str(ctx) + "_RAM");
+            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_RAM"), ci->name.str(ctx) + "_RAM");
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
             for (auto param : ci->params)
                 packed->params[param.first] = param.second;
             packed->params[ctx->id("NEG_CLK_W")] =
-                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNW") ||
-                                   ci->type == ctx->id("SB_RAM40_4KNRNW"));
+                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNW") || ci->type == ctx->id("SB_RAM40_4KNRNW"));
             packed->params[ctx->id("NEG_CLK_R")] =
-                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNR") ||
-                                   ci->type == ctx->id("SB_RAM40_4KNRNW"));
+                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNR") || ci->type == ctx->id("SB_RAM40_4KNRNW"));
             packed->type = ctx->id("ICESTORM_RAM");
             for (auto port : ci->ports) {
                 PortInfo &pi = port.second;
                 std::string newname = pi.name.str(ctx);
                 size_t bpos = newname.find('[');
                 if (bpos != std::string::npos) {
-                    newname = newname.substr(0, bpos) + "_" +
-                              newname.substr(bpos + 1,
-                                             (newname.size() - bpos) - 2);
+                    newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
-                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed,
-                             ctx->id(newname));
+                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed, ctx->id(newname));
             }
         }
     }
@@ -243,18 +218,15 @@ static void pack_ram(Context *ctx)
 }
 
 // Merge a net into a constant net
-static void set_net_constant(const Context *ctx, NetInfo *orig,
-                             NetInfo *constnet, bool constval)
+static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
 {
     orig->driver.cell = nullptr;
     for (auto user : orig->users) {
         if (user.cell != nullptr) {
             CellInfo *uc = user.cell;
             if (ctx->verbose)
-                log_info("%s user %s\n", orig->name.c_str(ctx),
-                         uc->name.c_str(ctx));
-            if ((is_lut(ctx, uc) || is_lc(ctx, uc)) &&
-                (user.port.str(ctx).at(0) == 'I') && !constval) {
+                log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
+            if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
                 uc->ports[user.port].net = nullptr;
             } else {
                 uc->ports[user.port].net = constnet;
@@ -270,16 +242,14 @@ static void pack_constants(Context *ctx)
 {
     log_info("Packing constants..\n");
 
-    CellInfo *gnd_cell =
-            create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
+    CellInfo *gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
     gnd_cell->params[ctx->id("LUT_INIT")] = "0";
     NetInfo *gnd_net = new NetInfo;
     gnd_net->name = ctx->id("$PACKER_GND_NET");
     gnd_net->driver.cell = gnd_cell;
     gnd_net->driver.port = ctx->id("O");
 
-    CellInfo *vcc_cell =
-            create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
+    CellInfo *vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
     vcc_cell->params[ctx->id("LUT_INIT")] = "1";
     NetInfo *vcc_net = new NetInfo;
     vcc_net->name = ctx->id("$PACKER_VCC_NET");
@@ -292,13 +262,11 @@ static void pack_constants(Context *ctx)
 
     for (auto net : sorted(ctx->nets)) {
         NetInfo *ni = net.second;
-        if (ni->driver.cell != nullptr &&
-            ni->driver.cell->type == ctx->id("GND")) {
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
             set_net_constant(ctx, ni, gnd_net, false);
             gnd_used = true;
             dead_nets.push_back(net.first);
-        } else if (ni->driver.cell != nullptr &&
-                   ni->driver.cell->type == ctx->id("VCC")) {
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
             set_net_constant(ctx, ni, vcc_net, true);
             vcc_used = true;
             dead_nets.push_back(net.first);
@@ -321,8 +289,7 @@ static void pack_constants(Context *ctx)
 
 static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 {
-    return cell->type == ctx->id("$nextpnr_ibuf") ||
-           cell->type == ctx->id("$nextpnr_obuf") ||
+    return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
            cell->type == ctx->id("$nextpnr_iobuf");
 }
 
@@ -338,22 +305,16 @@ static void pack_io(Context *ctx)
         CellInfo *ci = cell.second;
         if (is_nextpnr_iob(ctx, ci)) {
             CellInfo *sb = nullptr;
-            if (ci->type == ctx->id("$nextpnr_ibuf") ||
-                ci->type == ctx->id("$nextpnr_iobuf")) {
-                sb = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net,
-                                     is_sb_io, ctx->id("PACKAGE_PIN"), true,
-                                     ci);
+            if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
+                sb = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_sb_io, ctx->id("PACKAGE_PIN"), true, ci);
 
             } else if (ci->type == ctx->id("$nextpnr_obuf")) {
-                sb = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net,
-                                     is_sb_io, ctx->id("PACKAGE_PIN"), true,
-                                     ci);
+                sb = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_sb_io, ctx->id("PACKAGE_PIN"), true, ci);
             }
             if (sb != nullptr) {
                 // Trivial case, SB_IO used. Just destroy the net and the
                 // iobuf
-                log_info("%s feeds SB_IO %s, removing %s %s.\n",
-                         ci->name.c_str(ctx), sb->name.c_str(ctx),
+                log_info("%s feeds SB_IO %s, removing %s %s.\n", ci->name.c_str(ctx), sb->name.c_str(ctx),
                          ci->type.c_str(ctx), ci->name.c_str(ctx));
                 NetInfo *net = sb->ports.at(ctx->id("PACKAGE_PIN")).net;
                 if (net != nullptr) {
@@ -362,14 +323,12 @@ static void pack_io(Context *ctx)
                 }
             } else {
                 // Create a SB_IO buffer
-                sb = create_ice_cell(ctx, ctx->id("SB_IO"),
-                                     ci->name.str(ctx) + "$sb_io");
+                sb = create_ice_cell(ctx, ctx->id("SB_IO"), ci->name.str(ctx) + "$sb_io");
                 nxio_to_sb(ctx, ci, sb);
                 new_cells.push_back(sb);
             }
             packed_cells.insert(ci->name);
-            std::copy(ci->attrs.begin(), ci->attrs.end(),
-                      std::inserter(sb->attrs, sb->attrs.begin()));
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin()));
         }
     }
     for (auto pcell : packed_cells) {
@@ -380,11 +339,9 @@ static void pack_io(Context *ctx)
     }
 }
 
-static void insert_global(Context *ctx, NetInfo *net, bool is_reset,
-                          bool is_cen)
+static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen)
 {
-    std::string glb_name = net->name.str(ctx) + std::string("_$glb_") +
-                           (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
+    std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
     CellInfo *gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name);
     gb->ports[ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER")].net = net;
     PortRef pr;
@@ -401,8 +358,7 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset,
     gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet;
     std::vector<PortRef> keep_users;
     for (auto user : net->users) {
-        if (is_clock_port(ctx, user) ||
-            (is_reset && is_reset_port(ctx, user)) ||
+        if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) ||
             (is_cen && is_enable_port(ctx, user))) {
             user.cell->ports[user.port].net = glbnet;
             glbnet->users.push_back(user);
@@ -443,25 +399,19 @@ static void promote_globals(Context *ctx)
         if (is_gbuf(ctx, cell.second))
             --gbs_available;
     while (prom_globals < gbs_available) {
-        auto global_clock =
-                std::max_element(clock_count.begin(), clock_count.end(),
-                                 [](const std::pair<IdString, int> &a,
-                                    const std::pair<IdString, int> &b) {
-                                     return a.second < b.second;
-                                 });
-
-        auto global_reset =
-                std::max_element(reset_count.begin(), reset_count.end(),
-                                 [](const std::pair<IdString, int> &a,
-                                    const std::pair<IdString, int> &b) {
-                                     return a.second < b.second;
-                                 });
-        auto global_cen =
-                std::max_element(cen_count.begin(), cen_count.end(),
-                                 [](const std::pair<IdString, int> &a,
-                                    const std::pair<IdString, int> &b) {
-                                     return a.second < b.second;
-                                 });
+        auto global_clock = std::max_element(clock_count.begin(), clock_count.end(),
+                                             [](const std::pair<IdString, int> &a, const std::pair<IdString, int> &b) {
+                                                 return a.second < b.second;
+                                             });
+
+        auto global_reset = std::max_element(reset_count.begin(), reset_count.end(),
+                                             [](const std::pair<IdString, int> &a, const std::pair<IdString, int> &b) {
+                                                 return a.second < b.second;
+                                             });
+        auto global_cen = std::max_element(cen_count.begin(), cen_count.end(),
+                                           [](const std::pair<IdString, int> &a, const std::pair<IdString, int> &b) {
+                                               return a.second < b.second;
+                                           });
         if (global_reset->second > global_clock->second && prom_resets < 4) {
             NetInfo *rstnet = ctx->nets[global_reset->first];
             insert_global(ctx, rstnet, true, false);
@@ -502,15 +452,13 @@ static void pack_intosc(Context *ctx)
     for (auto cell : sorted(ctx->cells)) {
         CellInfo *ci = cell.second;
         if (is_sb_lfosc(ctx, ci)) {
-            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"),
-                                               ci->name.str(ctx) + "_OSC");
+            CellInfo *packed = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"), ci->name.str(ctx) + "_OSC");
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
             replace_port(ci, ctx->id("CLKLFEN"), packed, ctx->id("CLKLFEN"));
             replace_port(ci, ctx->id("CLKLFPU"), packed, ctx->id("CLKLFPU"));
             if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) {
-                replace_port(ci, ctx->id("CLKLF"), packed,
-                             ctx->id("CLKLF_FABRIC"));
+                replace_port(ci, ctx->id("CLKLF"), packed, ctx->id("CLKLF_FABRIC"));
             } else {
                 replace_port(ci, ctx->id("CLKLF"), packed, ctx->id("CLKLF"));
             }
diff --git a/ice40/pcf.cc b/ice40/pcf.cc
index 51f67364..ac1c8598 100644
--- a/ice40/pcf.cc
+++ b/ice40/pcf.cc
@@ -47,8 +47,7 @@ bool apply_pcf(Context *ctx, std::istream &in)
             std::string cmd = words.at(0);
             if (cmd == "set_io") {
                 size_t args_end = 1;
-                while (args_end < words.size() &&
-                       words.at(args_end).at(0) == '-')
+                while (args_end < words.size() && words.at(args_end).at(0) == '-')
                     args_end++;
                 std::string cell = words.at(args_end);
                 std::string pin = words.at(args_end + 1);
@@ -58,10 +57,8 @@ bool apply_pcf(Context *ctx, std::istream &in)
                 } else {
                     BelId pin_bel = ctx->getPackagePinBel(pin);
                     if (pin_bel == BelId())
-                        log_error("package does not have a pin named %s\n",
-                                  pin.c_str());
-                    fnd_cell->second->attrs[ctx->id("BEL")] =
-                            ctx->getBelName(pin_bel).str(ctx);
+                        log_error("package does not have a pin named %s\n", pin.c_str());
+                    fnd_cell->second->attrs[ctx->id("BEL")] = ctx->getBelName(pin_bel).str(ctx);
                     log_info("constrained '%s' to bel '%s'\n", cell.c_str(),
                              fnd_cell->second->attrs[ctx->id("BEL")].c_str());
                 }
diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc
index 2acc5258..4c707e65 100644
--- a/ice40/pybindings.cc
+++ b/ice40/pybindings.cc
@@ -45,9 +45,7 @@ void arch_wrap_python()
 
     class_<PipId>("PipId").def_readwrite("index", &PipId::index);
 
-    class_<BelPin>("BelPin")
-            .def_readwrite("bel", &BelPin::bel)
-            .def_readwrite("pin", &BelPin::pin);
+    class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
 
     enum_<PortPin>("PortPin")
 #define X(t) .value("PIN_" #t, PIN_##t)