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| author | myrtle <gatecat@ds0.me> | 2022-12-07 16:19:55 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-07 16:19:55 +0100 |
| commit | 0eb53d59d84ea1c46de7d9e25eb5a9901544202d (patch) | |
| tree | aa7203b5b1064f327b863e7d4cb025b6292c55e4 /ice40 | |
| parent | 519011533a3b7582b984226536cb424d462d1599 (diff) | |
| parent | df99b4ff6c5ce88ce1a731dc8682ab1875b8c237 (diff) | |
| download | nextpnr-0eb53d59d84ea1c46de7d9e25eb5a9901544202d.tar.gz nextpnr-0eb53d59d84ea1c46de7d9e25eb5a9901544202d.tar.bz2 nextpnr-0eb53d59d84ea1c46de7d9e25eb5a9901544202d.zip | |
Merge pull request #1059 from YosysHQ/gatecat/validity-errors
Add new option for verbose validity errors, use for ice40
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.h | 2 | ||||
| -rw-r--r-- | ice40/arch_place.cc | 28 |
2 files changed, 24 insertions, 6 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 9d10cddf..d80d6f64 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -840,7 +840,7 @@ struct Arch : BaseArch<ArchRanges> // implemented in arch_place.cc) // Return true whether all Bels at a given location are valid - bool isBelLocationValid(BelId bel) const override; + bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override; // Helper function for above bool logic_cells_compatible(const CellInfo **it, const size_t size) const; diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 5c3fa3c5..1d69d62f 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -82,7 +82,7 @@ static inline bool _io_pintype_need_clk_en(unsigned pin_type) return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type); } -bool Arch::isBelLocationValid(BelId bel) const +bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const { if (getBelType(bel) == id_ICESTORM_LC) { std::array<const CellInfo *, 8> bel_cells; @@ -124,6 +124,8 @@ bool Arch::isBelLocationValid(BelId bel) const return true; // Conflict + if (explain_invalid) + log_nonfatal_error("Cell '%s' conflicts with PLL cell '%s'\n", nameOf(cell), nameOf(pll_cell)); return false; } } @@ -135,18 +137,29 @@ bool Arch::isBelLocationValid(BelId bel) const // Check LVDS pairing if (cell->ioInfo.lvds) { // Check correct z and complement location is free - if (ioLoc.z != 0) + if (ioLoc.z != 0) { + if (explain_invalid) + log_nonfatal_error("Bel '%s' can't be used for LVDS\n", getCtx()->nameOfBel(bel)); return false; + } BelId compBel = getBelByLocation(compLoc); CellInfo *compCell = getBoundBelCell(compBel); - if (compCell) + if (compCell) { + if (explain_invalid) + log_nonfatal_error("Cell '%s' LVDS complement occupied by cell '%s'\n", nameOf(cell), + nameOf(compCell)); return false; + } } else { // Check LVDS IO is not placed at complement location BelId compBel = getBelByLocation(compLoc); const CellInfo *compCell = getBoundBelCell(compBel); - if (compCell && compCell->ioInfo.lvds) + if (compCell && compCell->ioInfo.lvds) { + if (explain_invalid) + log_nonfatal_error("Cell '%s' can't occupy LVDS complement of cell '%s'\n", nameOf(cell), + nameOf(compCell)); return false; + } // Check for conflicts on shared nets // - CLOCK_ENABLE @@ -168,8 +181,13 @@ bool Arch::isBelLocationValid(BelId bel) const }; for (int i = 0; i < 6; i++) - if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) + if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) { + if (explain_invalid) + log_nonfatal_error("Net '%s' for cell '%s' conflicts with net '%s' for '%s'\n", + nameOf(nets[i]), nameOf(cell), nameOf(nets[i ^ 1]), + nameOf(compCell)); return false; + } } } |