diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-09-25 18:15:00 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-09-25 18:15:00 +0200 |
| commit | 1eb7411fb0b814c524b83dc3c16715a814db8f5d (patch) | |
| tree | 5be59365e7420c403ab4c2090ccc11098737bc6a /ice40 | |
| parent | f1aa7093feed385e83266b0221672cae28b3365f (diff) | |
| parent | bbfe0f969d44338f1cdeae916544d0a974a8529e (diff) | |
| download | nextpnr-1eb7411fb0b814c524b83dc3c16715a814db8f5d.tar.gz nextpnr-1eb7411fb0b814c524b83dc3c16715a814db8f5d.tar.bz2 nextpnr-1eb7411fb0b814c524b83dc3c16715a814db8f5d.zip | |
Merge pull request #76 from YosysHQ/plloutglobal_fix
Add needed PLLOUTGLOBAL ports and mapped it
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/cells.cc | 2 | ||||
| -rw-r--r-- | ice40/pack.cc | 38 |
2 files changed, 38 insertions, 2 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc index e79a1fda..1c1e7a05 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -243,6 +243,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri add_port(ctx, new_cell.get(), "LOCK", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_B", PORT_OUT); + add_port(ctx, new_cell.get(), "PLLOUTGLOBALA", PORT_OUT); + add_port(ctx, new_cell.get(), "PLLOUTGLOBALB", PORT_OUT); } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } diff --git a/ice40/pack.cc b/ice40/pack.cc index 45d1489f..01cb3855 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -717,6 +717,30 @@ static void pack_special(Context *ctx) NetInfo *pad_packagepin_net = nullptr; + int pllout_a_used = 0; + int pllout_b_used = 0; + for (auto port : ci->ports) { + PortInfo &pi = port.second; + if (pi.name == ctx->id("PLLOUTCOREA")) + pllout_a_used++; + if (pi.name == ctx->id("PLLOUTCOREB")) + pllout_b_used++; + if (pi.name == ctx->id("PLLOUTCORE")) + pllout_a_used++; + if (pi.name == ctx->id("PLLOUTGLOBALA")) + pllout_a_used++; + if (pi.name == ctx->id("PLLOUTGLOBALB")) + pllout_b_used++; + if (pi.name == ctx->id("PLLOUTGLOBAL")) + pllout_a_used++; + } + + if (pllout_a_used > 1) + log_error("PLL '%s' is using multiple ports mapping to PLLOUT_A output of the PLL\n", ci->name.c_str(ctx)); + + if (pllout_b_used > 1) + log_error("PLL '%s' is using multiple ports mapping to PLLOUT_B output of the PLL\n", ci->name.c_str(ctx)); + for (auto port : ci->ports) { PortInfo &pi = port.second; std::string newname = pi.name.str(ctx); @@ -730,10 +754,20 @@ static void pack_special(Context *ctx) newname = "PLLOUT_B"; if (pi.name == ctx->id("PLLOUTCORE")) newname = "PLLOUT_A"; + if (pi.name == ctx->id("PLLOUTGLOBALA")) + newname = "PLLOUT_A"; + if (pi.name == ctx->id("PLLOUTGLOBALB")) + newname = "PLLOUT_B"; + if (pi.name == ctx->id("PLLOUTGLOBAL")) + newname = "PLLOUT_A"; + + if (pi.name == ctx->id("PLLOUTGLOBALA") || pi.name == ctx->id("PLLOUTGLOBALB") || pi.name == ctx->id("PLLOUTGLOBAL")) + log_warning("PLL '%s' is using port %s but implementation does not actually " + "use the global clock output of the PLL\n", ci->name.c_str(ctx), pi.name.str(ctx).c_str()); if (pi.name == ctx->id("PACKAGEPIN")) { if (!is_pad) { - log_error("PLL '%s' has a PACKAGEPIN but is not a PAD PLL", ci->name.c_str(ctx)); + log_error("PLL '%s' has a PACKAGEPIN but is not a PAD PLL\n", ci->name.c_str(ctx)); } else { // We drop this port and instead place the PLL adequately below. pad_packagepin_net = port.second.net; @@ -743,7 +777,7 @@ static void pack_special(Context *ctx) } if (pi.name == ctx->id("REFERENCECLK")) { if (!is_core) - log_error("PLL '%s' has a REFERENCECLK but is not a CORE PLL", ci->name.c_str(ctx)); + log_error("PLL '%s' has a REFERENCECLK but is not a CORE PLL\n", ci->name.c_str(ctx)); } if (packed->ports.count(ctx->id(newname)) == 0) { |