Improve iCE40 gfx for IO tiles and RAM tiles

Signed-off-by: Clifford Wolf <clifford@clifford.at>

5 files changed, 243 insertions, 23 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index c70ba4a3..58789043 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -342,15 +342,19 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     std::vector<std::pair<IdString, std::string>> ret;
     auto &wi = chip_info->wire_data[wire.index];
 
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wi.netidx)));
+
     ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
     ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
     ret.push_back(std::make_pair(id("GRID_Z"), stringf("%d", wi.z)));
 
+#if 0
     for (int i = 0; i < wi.num_segments; i++) {
         auto &si = wi.segments[i];
         ret.push_back(std::make_pair(id(stringf("segment[%d]", i)),
                                      stringf("X%d/Y%d/%s", si.x, si.y, chip_info->tile_wire_names[si.index].get())));
     }
+#endif
 
     return ret;
 }
@@ -760,7 +764,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
             GraphicElement el;
             el.type = GraphicElement::TYPE_BOX;
             el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
-            el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
+            el.x1 = chip_info->bel_data[bel.index].x + lut_swbox_x1;
             el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
             el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 +
                     (4 * chip_info->bel_data[bel.index].z) * logic_cell_pitch;
@@ -774,7 +778,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
                 GraphicElement el;
                 el.type = GraphicElement::TYPE_BOX;
                 el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
-                el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
+                el.x1 = chip_info->bel_data[bel.index].x + lut_swbox_x1;
                 el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
                 el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + i;
                 el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + i + 7 * logic_cell_pitch;
diff --git a/ice40/arch.h b/ice40/arch.h
index efdcc188..7f61c376 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -108,6 +108,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     };
 
     RelPtr<char> name;
+    int32_t netidx;
+
     int32_t num_uphill, num_downhill;
     RelPtr<int32_t> pips_uphill, pips_downhill;
 
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index cffeb657..5924f74a 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -96,6 +96,128 @@ with open(args.gfxh) as f:
             gfx_wire_ids[name] = idx
             gfx_wire_names.append(name)
 
+def gfx_wire_alias(old, new):
+    assert old in gfx_wire_ids
+    assert new not in gfx_wire_ids
+    gfx_wire_ids[new] = gfx_wire_ids[old]
+
+# GFX aliases for RAM tiles
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_RAM_RADDR_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_RAM_RADDR_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_2", "TILE_WIRE_RAM_RADDR_2")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_RAM_RADDR_3")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_0", "TILE_WIRE_RAM_RADDR_4")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_1", "TILE_WIRE_RAM_RADDR_5")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_2", "TILE_WIRE_RAM_RADDR_6")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_3", "TILE_WIRE_RAM_RADDR_7")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_0", "TILE_WIRE_RAM_RADDR_8")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_1", "TILE_WIRE_RAM_RADDR_9")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_2", "TILE_WIRE_RAM_RADDR_10")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_RAM_WADDR_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_RAM_WADDR_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_2", "TILE_WIRE_RAM_WADDR_2")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_RAM_WADDR_3")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_0", "TILE_WIRE_RAM_WADDR_4")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_1", "TILE_WIRE_RAM_WADDR_5")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_2", "TILE_WIRE_RAM_WADDR_6")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_3", "TILE_WIRE_RAM_WADDR_7")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_0", "TILE_WIRE_RAM_WADDR_8")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_1", "TILE_WIRE_RAM_WADDR_9")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_2", "TILE_WIRE_RAM_WADDR_10")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_0", "TILE_WIRE_RAM_MASK_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_1", "TILE_WIRE_RAM_MASK_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_2", "TILE_WIRE_RAM_MASK_2")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_3", "TILE_WIRE_RAM_MASK_3")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_RAM_MASK_4")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_RAM_MASK_5")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_2", "TILE_WIRE_RAM_MASK_6")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_RAM_MASK_7")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_0", "TILE_WIRE_RAM_MASK_8")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_1", "TILE_WIRE_RAM_MASK_9")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_2", "TILE_WIRE_RAM_MASK_10")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_3", "TILE_WIRE_RAM_MASK_11")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_RAM_MASK_12")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_RAM_MASK_13")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_2", "TILE_WIRE_RAM_MASK_14")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_RAM_MASK_15")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_0", "TILE_WIRE_RAM_WDATA_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_1", "TILE_WIRE_RAM_WDATA_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_2", "TILE_WIRE_RAM_WDATA_2")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_3", "TILE_WIRE_RAM_WDATA_3")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_0", "TILE_WIRE_RAM_WDATA_4")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_1", "TILE_WIRE_RAM_WDATA_5")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_2", "TILE_WIRE_RAM_WDATA_6")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_3", "TILE_WIRE_RAM_WDATA_7")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_0", "TILE_WIRE_RAM_WDATA_8")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_1", "TILE_WIRE_RAM_WDATA_9")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_2", "TILE_WIRE_RAM_WDATA_10")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_3", "TILE_WIRE_RAM_WDATA_11")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_0", "TILE_WIRE_RAM_WDATA_12")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_1", "TILE_WIRE_RAM_WDATA_13")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_2", "TILE_WIRE_RAM_WDATA_14")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_3", "TILE_WIRE_RAM_WDATA_15")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_RAM_RDATA_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_RAM_RDATA_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_OUT", "TILE_WIRE_RAM_RDATA_2")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_OUT", "TILE_WIRE_RAM_RDATA_3")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_RAM_RDATA_4")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_RAM_RDATA_5")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_OUT", "TILE_WIRE_RAM_RDATA_6")
+gfx_wire_alias("TILE_WIRE_LUTFF_7_OUT", "TILE_WIRE_RAM_RDATA_7")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_RAM_RDATA_8")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_RAM_RDATA_9")
+gfx_wire_alias("TILE_WIRE_LUTFF_2_OUT", "TILE_WIRE_RAM_RDATA_10")
+gfx_wire_alias("TILE_WIRE_LUTFF_3_OUT", "TILE_WIRE_RAM_RDATA_11")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_RAM_RDATA_12")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_RAM_RDATA_13")
+gfx_wire_alias("TILE_WIRE_LUTFF_6_OUT", "TILE_WIRE_RAM_RDATA_14")
+gfx_wire_alias("TILE_WIRE_LUTFF_7_OUT", "TILE_WIRE_RAM_RDATA_15")
+
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_RAM_RCLKE")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_RAM_WCLKE")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_RAM_RCLK")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_RAM_WCLK")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_RAM_RE")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_RAM_WE")
+
+# GFX aliases for IO tiles
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_IO_0_D_OUT_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_IO_0_D_OUT_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_IO_0_OUT_ENB")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_IO_0_D_IN_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_IO_0_D_IN_1")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_IO_1_D_OUT_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_IO_1_D_OUT_1")
+gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_IO_1_OUT_ENB")
+
+gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_IO_1_D_IN_0")
+gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_IO_1_D_IN_1")
+
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_IO_GLOBAL_CEN")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_IO_GLOBAL_INCLK")
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_IO_GLOBAL_OUTCLK")
+
+gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_G0", "TILE_WIRE_IO_GLOBAL_LATCH")
+
 def read_timings(filename):
     db = dict()
     with open(filename) as f:
@@ -167,6 +289,18 @@ def maj_wire_name(name):
         return name[2] in ("sp12_v_b_0", "sp12_v_b_1")
     return False
 
+def norm_wire_xy(x, y, name):
+    if name.startswith("glb_netwk_"):
+        return None
+    if name.startswith("neigh_op_"):
+        return None
+    if name.startswith("logic_op_"):
+        return None
+    if name.startswith("io_global/latch"):
+        return None
+    return None # FIXME
+    return (x, y)
+
 def cmp_wire_names(newname, oldname):
     if maj_wire_name(newname):
         return True
@@ -510,11 +644,13 @@ with open(args.filename, "r") as f:
                 wire_names_r[mode[1]] = wname
             if mode[1] not in wire_xy:
                 wire_xy[mode[1]] = list()
-            wire_xy[mode[1]].append((int(line[0]), int(line[1])))
+            wire_xy[mode[1]].append(wname)
             if mode[1] not in wire_segments:
                 wire_segments[mode[1]] = dict()
             if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids:
-                wire_segments[mode[1]][(wname[0], wname[1])] = wname[2]
+                if (wname[0], wname[1]) not in wire_segments[mode[1]]:
+                    wire_segments[mode[1]][(wname[0], wname[1])] = list()
+                wire_segments[mode[1]][(wname[0], wname[1])].append(wname[2])
             continue
 
         if mode[0] in ("buffer", "routing"):
@@ -563,7 +699,9 @@ def add_wire(x, y, name):
     wire_names_r[wire_idx] = wname
     wire_segments[wire_idx] = dict()
     if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids:
-        wire_segments[wire_idx][(wname[0], wname[1])] = wname[2]
+        if (wname[0], wname[1]) not in wire_segments[wire_idx]:
+            wire_segments[wire_idx][(wname[0], wname[1])] = list()
+        wire_segments[wire_idx][(wname[0], wname[1])].append(wname[2])
     return wire_idx
 
 def add_switch(x, y, bel=-1):
@@ -1034,20 +1172,32 @@ for wire in range(num_wires):
     info["num_bel_pins"] = num_bel_pins
     info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
 
-    if wire in wire_xy:
-        avg_x, avg_y = 0, 0
+    pos_xy = None
+    first = None
 
-        for x, y in wire_xy[wire]:
-            avg_x += x
-            avg_y += y
-        avg_x /= len(wire_xy[wire])
-        avg_y /= len(wire_xy[wire])
+    if wire in wire_xy:
+        for x, y, n in wire_xy[wire]:
+            norm_xy = norm_wire_xy(x, y, n)
+            if norm_xy is None:
+                continue
+            if pos_xy is None:
+                pos_xy = norm_xy
+                first = (x, y, n)
+            elif pos_xy != norm_xy:
+                print("Conflicting positions for wire %s: (%d, %d, %s) -> (%d, %d), (%d, %d, %s) -> (%d, %d)" % \
+                        ((info["name"],) + first + pos_xy + (x, y, n) + norm_xy), file=sys.stderr)
+                assert 0
+        if (pos_xy is None) and (len(wire_xy[wire]) > 1):
+                # print("Only 'None' positions for wire %s." % info["name"], file=sys.stderr)
+                # assert 0
+                pass
 
-        info["x"] = int(round(avg_x))
-        info["y"] = int(round(avg_y))
-    else:
+    if pos_xy is None:
         info["x"] = wire_names_r[wire][0]
         info["y"] = wire_names_r[wire][1]
+    else:
+        info["x"] = pos_xy[0]
+        info["y"] = pos_xy[1]
 
     wireinfo.append(info)
 
@@ -1108,14 +1258,21 @@ for t in range(num_tile_types):
 bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
 for wire, info in enumerate(wireinfo):
     bba.s(info["name"], "name")
+    bba.u32(wire, "netidx")
+
     bba.u32(info["num_uphill"], "num_uphill")
     bba.u32(info["num_downhill"], "num_downhill")
     bba.r(info["list_uphill"], "pips_uphill")
     bba.r(info["list_downhill"], "pips_downhill")
     bba.u32(info["num_bel_pins"], "num_bel_pins")
     bba.r(info["list_bel_pins"], "bel_pins")
-    bba.u32(len(wire_segments[wire]), "num_segments")
-    if len(wire_segments[wire]):
+
+    num_segments = 0
+    for segs in wire_segments[wire].values():
+        num_segments += len(segs)
+    bba.u32(num_segments, "num_segments")
+
+    if num_segments:
         bba.r("wire_segments_%d" % wire, "segments")
     else:
         bba.u32(0, "segments")
@@ -1131,24 +1288,25 @@ for wire, info in enumerate(wireinfo):
 for wire in range(num_wires):
     if len(wire_segments[wire]):
         bba.l("wire_segments_%d" % wire, "WireSegmentPOD")
-        for xy, seg in sorted(wire_segments[wire].items()):
-            bba.u8(xy[0], "x")
-            bba.u8(xy[1], "y")
-            bba.u16(gfx_wire_ids["TILE_WIRE_" + seg.upper().replace("/", "_")], "index")
+        for xy, segs in sorted(wire_segments[wire].items()):
+            for seg in segs:
+                bba.u8(xy[0], "x")
+                bba.u8(xy[1], "y")
+                bba.u16(gfx_wire_ids["TILE_WIRE_" + seg.upper().replace("/", "_")], "index")
 
 bba.l("pip_data_%s" % dev_name, "PipInfoPOD")
 for info in pipinfo:
     src_seg = -1
     src_segname = wire_names_r[info["src"]]
     if (info["x"], info["y"]) in wire_segments[info["src"]]:
-        src_segname = wire_segments[info["src"]][(info["x"], info["y"])]
+        src_segname = wire_segments[info["src"]][(info["x"], info["y"])][0]
         src_seg = gfx_wire_ids["TILE_WIRE_" + src_segname.upper().replace("/", "_")]
         src_segname = src_segname.replace("/", ".")
 
     dst_seg = -1
     dst_segname = wire_names_r[info["dst"]]
     if (info["x"], info["y"]) in wire_segments[info["dst"]]:
-        dst_segname = wire_segments[info["dst"]][(info["x"], info["y"])]
+        dst_segname = wire_segments[info["dst"]][(info["x"], info["y"])][0]
         dst_seg = gfx_wire_ids["TILE_WIRE_" + dst_segname.upper().replace("/", "_")]
         dst_segname = dst_segname.replace("/", ".")
 
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index 1ab2fb3c..11bf29eb 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -457,6 +457,42 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
         }
     }
 
+    // LC Control for IO and BRAM
+
+    if (id >= TILE_WIRE_FUNC_GLOBAL_CEN && id <= TILE_WIRE_FUNC_GLOBAL_S_R) {
+        int idx = id - TILE_WIRE_FUNC_GLOBAL_CEN;
+
+        el.x1 = x + main_swbox_x2 - 0.005 * (idx + 5);
+        el.x2 = el.x1;
+        el.y1 = y + main_swbox_y1;
+        el.y2 = el.y1 - 0.005 * (idx + 2);
+        g.push_back(el);
+
+        el.y1 = el.y2;
+        el.x2 = x + logic_cell_x2 - 0.005 * (2 - idx + 5);
+        g.push_back(el);
+
+        el.y2 = y + logic_cell_y1;
+        el.x1 = el.x2;
+        g.push_back(el);
+    }
+
+    if (id == TILE_WIRE_FABOUT) {
+        el.y1 = y + main_swbox_y1;
+        el.y2 = el.y1 - 0.005 * 4;
+        el.x1 = x + main_swbox_x2 - 0.005 * 9;
+        el.x2 = el.x1;
+        g.push_back(el);
+    }
+
+    if (id == TILE_WIRE_FUNC_GLOBAL_G0) {
+        el.y1 = y + logic_cell_y1;
+        el.y2 = el.y1 - 0.005 * 4;
+        el.x1 = x + logic_cell_x2 - 0.005 * 3;
+        el.x2 = el.x1;
+        g.push_back(el);
+    }
+
     // LC Cascade
 
     if (id >= TILE_WIRE_LUTFF_0_LOUT && id <= TILE_WIRE_LUTFF_6_LOUT) {
@@ -626,6 +662,19 @@ static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
         return true;
     }
 
+    if (id >= TILE_WIRE_FUNC_GLOBAL_CEN && id <= TILE_WIRE_FUNC_GLOBAL_S_R) {
+        int idx = id - TILE_WIRE_FUNC_GLOBAL_CEN;
+        x = main_swbox_x2 - 0.005 * (idx + 5);
+        y = main_swbox_y1;
+        return true;
+    }
+
+    if (id == TILE_WIRE_FABOUT) {
+        x = main_swbox_x2 - 0.005 * 9;
+        y = main_swbox_y1;
+        return true;
+    }
+
     return false;
 }
 
diff --git a/ice40/gfx.h b/ice40/gfx.h
index 8ee7b0b6..c4af090d 100644
--- a/ice40/gfx.h
+++ b/ice40/gfx.h
@@ -205,6 +205,13 @@ enum GfxTileWireId
     TILE_WIRE_LUTFF_GLOBAL_CLK,
     TILE_WIRE_LUTFF_GLOBAL_S_R,
 
+    TILE_WIRE_FUNC_GLOBAL_CEN,
+    TILE_WIRE_FUNC_GLOBAL_CLK,
+    TILE_WIRE_FUNC_GLOBAL_S_R,
+
+    TILE_WIRE_FUNC_GLOBAL_G0,
+    TILE_WIRE_FABOUT,
+
     TILE_WIRE_CARRY_IN,
     TILE_WIRE_CARRY_IN_MUX,