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author | David Shah <davey1576@gmail.com> | 2018-06-12 14:43:56 +0200 |
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committer | David Shah <davey1576@gmail.com> | 2018-06-12 14:43:56 +0200 |
commit | 592a627e0c99ddf2cf06c286813a2d08962d8cd9 (patch) | |
tree | 5da4e6d6c4bfdb3d5a600b365ed9cb856c307de9 /ice40 | |
parent | 5a9ff4aea15fca7bcf8c86eaa1f92eb51f551e5b (diff) | |
parent | c8b815361e2435bf12786705638908aa891df44f (diff) | |
download | nextpnr-592a627e0c99ddf2cf06c286813a2d08962d8cd9.tar.gz nextpnr-592a627e0c99ddf2cf06c286813a2d08962d8cd9.tar.bz2 nextpnr-592a627e0c99ddf2cf06c286813a2d08962d8cd9.zip |
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/arch_place.cc | 4 | ||||
-rw-r--r-- | ice40/arch_place.h | 4 | ||||
-rw-r--r-- | ice40/bitstream.cc | 4 | ||||
-rw-r--r-- | ice40/bitstream.h | 4 | ||||
-rw-r--r-- | ice40/cells.cc | 4 | ||||
-rw-r--r-- | ice40/cells.h | 4 | ||||
-rw-r--r-- | ice40/chip.cc | 4 | ||||
-rw-r--r-- | ice40/chip.h | 20 | ||||
-rw-r--r-- | ice40/chipdb.py | 9 | ||||
-rw-r--r-- | ice40/family.cmake | 1 | ||||
-rw-r--r-- | ice40/pack.cc | 4 | ||||
-rw-r--r-- | ice40/pack.h | 4 | ||||
-rw-r--r-- | ice40/pybindings.cc | 4 |
13 files changed, 63 insertions, 7 deletions
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 2367d981..dbc8036c 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -19,6 +19,8 @@ #include "arch_place.h" +NEXTPNR_NAMESPACE_BEGIN + static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) { bool dffs_exist = false, dffs_neg = false; @@ -87,3 +89,5 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) return true; } } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/arch_place.h b/ice40/arch_place.h index 8f8ce806..a505f4db 100644 --- a/ice40/arch_place.h +++ b/ice40/arch_place.h @@ -23,9 +23,13 @@ #include "nextpnr.h" // Architecure-specific placement functions +NEXTPNR_NAMESPACE_BEGIN + // Whether or not a given cell can be placed at a given Bel // This is not intended for Bel type checks, but finer-grained constraints // such as conflicting set/reset signals, etc bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel); +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 944e80c2..7952a8a1 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -20,6 +20,8 @@ #include "bitstream.h" #include <vector> +NEXTPNR_NAMESPACE_BEGIN + inline TileType tile_at(const Chip &chip, int x, int y) { return chip.chip_info.tile_grid[y * chip.chip_info.width + x]; @@ -311,3 +313,5 @@ void write_asc(const Design &design, std::ostream &out) } } } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/bitstream.h b/ice40/bitstream.h index fecc14e1..11547163 100644 --- a/ice40/bitstream.h +++ b/ice40/bitstream.h @@ -23,6 +23,10 @@ #include <iostream> #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + void write_asc(const Design &design, std::ostream &out); +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/cells.cc b/ice40/cells.cc index d187d492..004bdb30 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -21,6 +21,8 @@ #include "design_utils.h" #include "log.h" +NEXTPNR_NAMESPACE_BEGIN + static void add_port(CellInfo *cell, IdString name, PortType dir) { cell->ports[name] = PortInfo{name, nullptr, dir}; @@ -125,3 +127,5 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut) replace_port(dff, "Q", lc, "O"); } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/cells.h b/ice40/cells.h index a2d45df6..34a034cd 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -22,6 +22,8 @@ #ifndef ICE40_CELLS_H #define ICE40_CELLS_H +NEXTPNR_NAMESPACE_BEGIN + // Create a standard iCE40 cell and return it // Name will be automatically assigned if not specified CellInfo *create_ice_cell(Design *design, IdString type, @@ -56,4 +58,6 @@ void lut_to_lc(CellInfo *lut, CellInfo *lc, bool no_dff = true); // ignored void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false); +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/chip.cc b/ice40/chip.cc index 21beb648..88fcc512 100644 --- a/ice40/chip.cc +++ b/ice40/chip.cc @@ -20,6 +20,8 @@ #include "log.h" #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + // ----------------------------------------------------------------------- IdString belTypeToId(BelType type) @@ -347,3 +349,5 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const return ret; } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/chip.h b/ice40/chip.h index 097fb286..96416c04 100644 --- a/ice40/chip.h +++ b/ice40/chip.h @@ -24,6 +24,8 @@ #error Include "chip.h" via "nextpnr.h" only. #endif +NEXTPNR_NAMESPACE_BEGIN + struct DelayInfo { float delay = 0; @@ -210,32 +212,36 @@ struct BelPin PortPin pin; }; +NEXTPNR_NAMESPACE_END + namespace std { -template <> struct hash<BelId> +template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId> { - std::size_t operator()(const BelId &bel) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept { return bel.index; } }; -template <> struct hash<WireId> +template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId> { - std::size_t operator()(const WireId &wire) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept { return wire.index; } }; -template <> struct hash<PipId> +template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId> { - std::size_t operator()(const PipId &wire) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &wire) const noexcept { return wire.index; } }; } // namespace std +NEXTPNR_NAMESPACE_BEGIN + // ----------------------------------------------------------------------- struct BelIterator @@ -679,4 +685,6 @@ struct Chip std::vector<GraphicElement> getFrameGraphics() const; }; +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 34366679..9b246f8b 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -312,6 +312,8 @@ elif dev_name == "5k": add_bel_gb(19, 0, 7) print('#include "nextpnr.h"') +print('namespace {') +print('USING_NEXTPNR_NAMESPACE') for bel in range(len(bel_name)): print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel]))) @@ -319,7 +321,7 @@ for bel in range(len(bel_name)): print(" {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",))) print("};") -print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) +print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) for bel in range(len(bel_name)): print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel], len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2], @@ -458,8 +460,13 @@ print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid))) print(",\n".join(tilegrid)) print("};") +print('}') +print('NEXTPNR_NAMESPACE_BEGIN') + print("ChipInfoPOD chip_info_%s = {" % dev_name) print(" %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo))) print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name)) print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name)) print("};") + +print('NEXTPNR_NAMESPACE_END') diff --git a/ice40/family.cmake b/ice40/family.cmake index 33c5c20e..1ed2ecf3 100644 --- a/ice40/family.cmake +++ b/ice40/family.cmake @@ -11,6 +11,7 @@ set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py) file(MAKE_DIRECTORY ice40/chipdbs/) add_library(ice40_chipdb OBJECT ice40/chipdbs/) target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w) +target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) target_include_directories(ice40_chipdb PRIVATE ${family}/) foreach (dev ${devices}) set(DEV_TXT_DB /usr/local/share/icebox/chipdb-${dev}.txt) diff --git a/ice40/pack.cc b/ice40/pack.cc index ff421c17..a6e17378 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -25,6 +25,8 @@ #include <unordered_set> +NEXTPNR_NAMESPACE_BEGIN + // Pack LUTs and LUT-FF pairs static void pack_lut_lutffs(Design *design) { @@ -120,3 +122,5 @@ void pack_design(Design *design) pack_lut_lutffs(design); pack_nonlut_ffs(design); } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/pack.h b/ice40/pack.h index 87a390ff..4a92a7ab 100644 --- a/ice40/pack.h +++ b/ice40/pack.h @@ -22,6 +22,10 @@ #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + void pack_design(Design *design); +NEXTPNR_NAMESPACE_END + #endif // ROUTE_H diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc index c00bf6b9..9094fe7c 100644 --- a/ice40/pybindings.cc +++ b/ice40/pybindings.cc @@ -21,6 +21,8 @@ #include "pybindings.h" #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + void arch_wrap_python() { class_<ChipArgs>("ChipArgs").def_readwrite("type", &ChipArgs::type); @@ -80,3 +82,5 @@ void arch_wrap_python() WRAP_RANGE(AllPip); WRAP_RANGE(Pip); } + +NEXTPNR_NAMESPACE_END |