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authorgatecat <gatecat@ds0.me>2022-02-18 10:52:37 +0000
committergatecat <gatecat@ds0.me>2022-02-18 11:13:18 +0000
commit6a32aca4ac8705b637943c236cedd2f36422fb21 (patch)
tree28483964fb3c92bc104ab6162d1c9196651ced26 /ice40
parent61d1db16be2c68cf6ae8b4d2ff3266b5c7086ad2 (diff)
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refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ice40')
-rw-r--r--ice40/arch.cc14
-rw-r--r--ice40/cells.cc47
-rw-r--r--ice40/pack.cc36
3 files changed, 50 insertions, 47 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index cf7e99a5..b36c82d5 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -1219,17 +1219,17 @@ void Arch::assignCellInfo(CellInfo *cell)
cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
- cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
- cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
- cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
+ cell->lcInfo.clk = cell->getPort(id_CLK);
+ cell->lcInfo.cen = cell->getPort(id_CEN);
+ cell->lcInfo.sr = cell->getPort(id_SR);
cell->lcInfo.inputCount = 0;
- if (get_net_or_empty(cell, id_I0))
+ if (cell->getPort(id_I0))
cell->lcInfo.inputCount++;
- if (get_net_or_empty(cell, id_I1))
+ if (cell->getPort(id_I1))
cell->lcInfo.inputCount++;
- if (get_net_or_empty(cell, id_I2))
+ if (cell->getPort(id_I2))
cell->lcInfo.inputCount++;
- if (get_net_or_empty(cell, id_I3))
+ if (cell->getPort(id_I3))
cell->lcInfo.inputCount++;
} else if (cell->type == id_SB_IO) {
cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT";
diff --git a/ice40/cells.cc b/ice40/cells.cc
index a8d30347..b5f759b2 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -340,12 +340,12 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
if (lc->hierpath == IdString())
lc->hierpath = lut->hierpath;
lc->params[id_LUT_INIT] = lut->params[id_LUT_INIT].extract(0, 16, Property::State::S0);
- replace_port(lut, id_I0, lc, id_I0);
- replace_port(lut, id_I1, lc, id_I1);
- replace_port(lut, id_I2, lc, id_I2);
- replace_port(lut, id_I3, lc, id_I3);
+ lut->movePortTo(id_I0, lc, id_I0);
+ lut->movePortTo(id_I1, lc, id_I1);
+ lut->movePortTo(id_I2, lc, id_I2);
+ lut->movePortTo(id_I3, lc, id_I3);
if (no_dff) {
- replace_port(lut, id_O, lc, id_O);
+ lut->movePortTo(id_O, lc, id_O);
lc->params[id_DFF_ENABLE] = Property::State::S0;
}
}
@@ -357,7 +357,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
lc->params[id_DFF_ENABLE] = Property::State::S1;
std::string config = dff->type.str(ctx).substr(6);
auto citer = config.begin();
- replace_port(dff, id_C, lc, id_CLK);
+ dff->movePortTo(id_C, lc, id_CLK);
if (citer != config.end() && *citer == 'N') {
lc->params[id_NEG_CLK] = Property::State::S1;
@@ -367,7 +367,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
}
if (citer != config.end() && *citer == 'E') {
- replace_port(dff, id_E, lc, id_CEN);
+ dff->movePortTo(id_E, lc, id_CEN);
++citer;
}
@@ -382,12 +382,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (*citer == 'S') {
citer++;
- replace_port(dff, id_S, lc, id_SR);
+ dff->movePortTo(id_S, lc, id_SR);
lc->params[id_SET_NORESET] = Property::State::S1;
} else {
NPNR_ASSERT(*citer == 'R');
citer++;
- replace_port(dff, id_R, lc, id_SR);
+ dff->movePortTo(id_R, lc, id_SR);
lc->params[id_SET_NORESET] = Property::State::S0;
}
}
@@ -396,10 +396,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
if (pass_thru_lut) {
lc->params[id_LUT_INIT] = Property(2, 16);
- replace_port(dff, id_D, lc, id_I0);
+ dff->movePortTo(id_D, lc, id_I0);
}
- replace_port(dff, id_Q, lc, id_O);
+ dff->movePortTo(id_Q, lc, id_O);
}
void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells)
@@ -409,13 +409,13 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
auto pu_attr = nxio->attrs.find(id_PULLUP);
if (pu_attr != nxio->attrs.end())
sbio->params[id_PULLUP] = pu_attr->second;
- replace_port(nxio, id_O, sbio, id_D_IN_0);
+ nxio->movePortTo(id_O, sbio, id_D_IN_0);
} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
sbio->params[id_PIN_TYPE] = 25;
- replace_port(nxio, id_I, sbio, id_D_OUT_0);
+ nxio->movePortTo(id_I, sbio, id_D_OUT_0);
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
// N.B. tristate will be dealt with below
- NetInfo *i = get_net_or_empty(nxio, id_I);
+ NetInfo *i = nxio->getPort(id_I);
if (i == nullptr || i->driver.cell == nullptr)
sbio->params[id_PIN_TYPE] = 1;
else
@@ -423,8 +423,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
auto pu_attr = nxio->attrs.find(id_PULLUP);
if (pu_attr != nxio->attrs.end())
sbio->params[id_PULLUP] = pu_attr->second;
- replace_port(nxio, id_I, sbio, id_D_OUT_0);
- replace_port(nxio, id_O, sbio, id_D_IN_0);
+ nxio->movePortTo(id_I, sbio, id_D_OUT_0);
+ nxio->movePortTo(id_O, sbio, id_D_IN_0);
} else {
NPNR_ASSERT(false);
}
@@ -432,9 +432,11 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
// Rename I/O nets to avoid conflicts
if (donet != nullptr && donet->name == nxio->name)
- rename_net(ctx, donet, ctx->id(donet->name.str(ctx) + "$SB_IO_OUT"));
+ if (donet)
+ ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$SB_IO_OUT"));
if (dinet != nullptr && dinet->name == nxio->name)
- rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$SB_IO_IN"));
+ if (dinet)
+ ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$SB_IO_IN"));
if (ctx->nets.count(nxio->name)) {
int i = 0;
@@ -442,7 +444,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
do {
new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
} while (ctx->nets.count(new_name));
- rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+ if (ctx->nets.at(nxio->name).get())
+ ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name);
}
// Create a new top port net for accurate IO timing analysis and simulation netlists
@@ -451,7 +454,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
NPNR_ASSERT(!ctx->nets.count(tn_netname));
ctx->net_aliases.erase(tn_netname);
NetInfo *toplevel_net = ctx->createNet(tn_netname);
- connect_port(ctx, toplevel_net, sbio, id_PACKAGE_PIN);
+ sbio->connectPort(id_PACKAGE_PIN, toplevel_net);
ctx->ports[nxio->name].net = toplevel_net;
}
@@ -460,8 +463,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
id_Y);
if (tbuf) {
sbio->params[id_PIN_TYPE] = 41;
- replace_port(tbuf, id_A, sbio, id_D_OUT_0);
- replace_port(tbuf, id_E, sbio, id_OUTPUT_ENABLE);
+ tbuf->movePortTo(id_A, sbio, id_D_OUT_0);
+ tbuf->movePortTo(id_E, sbio, id_OUTPUT_ENABLE);
if (donet->users.size() > 1) {
for (auto user : donet->users)
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 0220d4fe..4244f192 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -227,8 +227,8 @@ static void pack_carries(Context *ctx)
++carry_only;
}
carry_lc->params[id_CARRY_ENABLE] = Property::State::S1;
- replace_port(ci, id_CI, carry_lc, id_CIN);
- replace_port(ci, id_CO, carry_lc, id_COUT);
+ ci->movePortTo(id_CI, carry_lc, id_CIN);
+ ci->movePortTo(id_CO, carry_lc, id_COUT);
if (i0_net) {
auto &i0_usrs = i0_net->users;
i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(), [ci, ctx](const PortRef &pr) {
@@ -300,7 +300,7 @@ static void pack_ram(Context *ctx)
newname = "RCLK";
else if (pi.name == id_WCLKN)
newname = "WCLK";
- replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+ ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
}
new_cells.push_back(std::move(packed));
}
@@ -442,7 +442,7 @@ static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell,
gb->attrs[id_BEL] = ctx->getBelName(gb_bel).str(ctx);
// Reconnect the net to that port for easier identification it's a global net
- replace_port(cell, port_name, gb.get(), id_GLOBAL_BUFFER_OUTPUT);
+ cell->movePortTo(port_name, gb.get(), id_GLOBAL_BUFFER_OUTPUT);
return gb;
}
@@ -514,7 +514,7 @@ static void pack_io(Context *ctx)
} else if (rgb != nullptr) {
log_info("%s use by SB_RGBA_DRV/SB_RGB_DRV %s, not creating SB_IO\n", ci->name.c_str(ctx),
rgb->name.c_str(ctx));
- disconnect_port(ctx, ci, id_I);
+ ci->disconnectPort(id_I);
packed_cells.insert(ci->name);
continue;
} else {
@@ -525,7 +525,7 @@ static void pack_io(Context *ctx)
sb = new_cells.back().get();
}
for (auto port : ci->ports)
- disconnect_port(ctx, ci, port.first);
+ ci->disconnectPort(port.first);
packed_cells.insert(ci->name);
for (auto &attr : ci->attrs)
sb->attrs[attr.first] = attr.second;
@@ -1138,13 +1138,13 @@ static void pack_special(Context *ctx)
std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_LFOSC, ci->name.str(ctx) + "_OSC");
packed_cells.insert(ci->name);
cell_place_unique(ctx, packed.get());
- replace_port(ci, id_CLKLFEN, packed.get(), id_CLKLFEN);
- replace_port(ci, id_CLKLFPU, packed.get(), id_CLKLFPU);
+ ci->movePortTo(id_CLKLFEN, packed.get(), id_CLKLFEN);
+ ci->movePortTo(id_CLKLFPU, packed.get(), id_CLKLFPU);
if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
- replace_port(ci, id_CLKLF, packed.get(), id_CLKLF_FABRIC);
+ ci->movePortTo(id_CLKLF, packed.get(), id_CLKLF_FABRIC);
set_period(ctx, packed.get(), id_CLKLF_FABRIC, 100000000); // 10kHz
} else {
- replace_port(ci, id_CLKLF, packed.get(), id_CLKLF);
+ ci->movePortTo(id_CLKLF, packed.get(), id_CLKLF);
std::unique_ptr<CellInfo> gb =
create_padin_gbuf(ctx, packed.get(), id_CLKLF, "$gbuf_" + ci->name.str(ctx) + "_lfosc");
set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 100000000); // 10kHz
@@ -1157,11 +1157,11 @@ static void pack_special(Context *ctx)
cell_place_unique(ctx, packed.get());
packed->params[id_TRIM_EN] = str_or_default(ci->params, id_TRIM_EN, "0b0");
packed->params[id_CLKHF_DIV] = str_or_default(ci->params, id_CLKHF_DIV, "0b00");
- replace_port(ci, id_CLKHFEN, packed.get(), id_CLKHFEN);
- replace_port(ci, id_CLKHFPU, packed.get(), id_CLKHFPU);
+ ci->movePortTo(id_CLKHFEN, packed.get(), id_CLKHFEN);
+ ci->movePortTo(id_CLKHFPU, packed.get(), id_CLKHFPU);
for (int i = 0; i < 10; i++) {
auto port = ctx->id("TRIM" + std::to_string(i));
- replace_port(ci, port, packed.get(), port);
+ ci->movePortTo(port, packed.get(), port);
}
std::string div = packed->params[id_CLKHF_DIV].as_string();
int frequency;
@@ -1176,10 +1176,10 @@ static void pack_special(Context *ctx)
else
log_error("Invalid HFOSC divider value '%s' - expecting 0b00, 0b01, 0b10 or 0b11\n", div.c_str());
if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
- replace_port(ci, id_CLKHF, packed.get(), id_CLKHF_FABRIC);
+ ci->movePortTo(id_CLKHF, packed.get(), id_CLKHF_FABRIC);
set_period(ctx, packed.get(), id_CLKHF_FABRIC, 1000000 / frequency);
} else {
- replace_port(ci, id_CLKHF, packed.get(), id_CLKHF);
+ ci->movePortTo(id_CLKHF, packed.get(), id_CLKHF);
std::unique_ptr<CellInfo> gb =
create_padin_gbuf(ctx, packed.get(), id_CLKHF, "$gbuf_" + ci->name.str(ctx) + "_hfosc");
set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 1000000 / frequency);
@@ -1198,7 +1198,7 @@ static void pack_special(Context *ctx)
if (bpos != std::string::npos) {
newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
}
- replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+ ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
}
new_cells.push_back(std::move(packed));
} else if (is_sb_mac16(ctx, ci)) {
@@ -1216,7 +1216,7 @@ static void pack_special(Context *ctx)
if (bpos != std::string::npos) {
newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
}
- replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+ ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
}
new_cells.push_back(std::move(packed));
} else if (is_sb_rgba_drv(ctx, ci) || is_sb_rgb_drv(ctx, ci)) {
@@ -1410,7 +1410,7 @@ void pack_plls(Context *ctx)
}
}
}
- replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+ ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
}
// Compute derive constraints