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authorClifford Wolf <clifford@clifford.at>2018-06-09 19:52:22 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-09 19:52:22 +0200
commit70f322ab449ce6786f1daacdc6c78df14a2ff5f5 (patch)
tree3db633702922e882770fd864b5609e7ae83aee41 /ice40
parent72f5e640af8bdccb641bb561757021c0a3d83edb (diff)
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Renamed LOC attribute to BEL, fix ice40 IO bel names
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40')
-rw-r--r--ice40/blinky.v16
-rw-r--r--ice40/chipdb.py2
2 files changed, 9 insertions, 9 deletions
diff --git a/ice40/blinky.v b/ice40/blinky.v
index 80f92b06..7fd3a0cf 100644
--- a/ice40/blinky.v
+++ b/ice40/blinky.v
@@ -7,8 +7,8 @@ module blinky (
output led5_pin
);
wire clk, led1, led2, led3, led4, led5;
-
- (* LOC="0_3_lc0" *)
+
+ (* BEL="13_12_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
@@ -25,8 +25,8 @@ module blinky (
.D_IN_0(),
.D_IN_1()
);
-
- (* LOC="0_3_lc1" *)
+
+ (* BEL="13_12_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
@@ -44,7 +44,7 @@ module blinky (
.D_IN_1()
);
- (* LOC="5_17_lc1" *)
+ (* BEL="13_11_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
@@ -62,7 +62,7 @@ module blinky (
.D_IN_1()
);
- (* LOC="10_0_lc1" *)
+ (* BEL="13_11_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
@@ -80,7 +80,7 @@ module blinky (
.D_IN_1()
);
- (* LOC="12_17_lc0" *)
+ (* BEL="13_9_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
@@ -98,7 +98,7 @@ module blinky (
.D_IN_1()
);
- (* LOC="0_6_lc0" *)
+ (* BEL="0_8_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 78ba2e46..b4240e2d 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -186,7 +186,7 @@ def add_bel_lc(x, y, z):
def add_bel_io(x, y, z):
bel = len(bel_name)
- bel_name.append("%d_%d_lc%d" % (x, y, z))
+ bel_name.append("%d_%d_io%d" % (x, y, z))
bel_type.append("SB_IO")
bel_pos.append((x, y, z))
bel_wires.append(list())