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authorDavid Shah <davey1576@gmail.com>2019-02-25 08:20:32 +0000
committerGitHub <noreply@github.com>2019-02-25 08:20:32 +0000
commit7a5699891a1a79a44f959c4d2337f2512c656ae2 (patch)
treeffadef56778f1acc3ffa47c66f2eb97045c68154 /ice40
parent8c7050191233265662b4e9f15d73c0e7de44c597 (diff)
parenta05f6b261ecf437f8618da6f7dc95d860b429edd (diff)
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Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires
ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
Diffstat (limited to 'ice40')
-rw-r--r--ice40/chipdb.py19
-rw-r--r--ice40/constids.inc5
2 files changed, 24 insertions, 0 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 824c3d94..93e340fb 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -954,6 +954,25 @@ def add_bel_ec(ec):
add_pll_clock_output(bel, ec, entry)
else:
extra_cell_config[bel].append(entry)
+ if ectype == "MAC16":
+ if y == 5:
+ last_dsp_y = 0 # dummy, but the wire is needed
+ elif y == 10:
+ last_dsp_y = 5
+ elif y == 15:
+ last_dsp_y = 10
+ elif y == 23:
+ last_dsp_y = 23
+ else:
+ assert False, "unknown DSP y " + str(y)
+ wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout")
+ wire_signextout = add_wire(x, y, "dsp/signextout")
+ wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco")
+ wire_accumco = add_wire(x, y, "dsp/accumco")
+ add_bel_input(bel, wire_signextin, "SIGNEXTIN")
+ add_bel_output(bel, wire_signextout, "SIGNEXTOUT")
+ add_bel_input(bel, wire_accumci, "ACCUMCI")
+ add_bel_output(bel, wire_accumco, "ACCUMCO")
cell_timings = {}
tmport_to_constids = {
diff --git a/ice40/constids.inc b/ice40/constids.inc
index 9e13f4ab..366a3a9d 100644
--- a/ice40/constids.inc
+++ b/ice40/constids.inc
@@ -247,6 +247,11 @@ X(O_6)
X(O_7)
X(O_8)
X(O_9)
+X(SIGNEXTIN)
+X(SIGNEXTOUT)
+X(ACCUMCI)
+X(ACCUMCO)
+
X(CLKHF)
X(CLKHFEN)